参数资料
型号: LT1976EFE#TR
厂商: Linear Technology
文件页数: 18/28页
文件大小: 0K
描述: IC REG BUCK ADJ 1.5A 16TSSOP
标准包装: 2,500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.2 V ~ 54 V
输入电压: 3.3 V ~ 60 V
PWM 型: 电流模式,混合
频率 - 开关: 200kHz
电流 - 输出: 1.5A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 16-TSSOP-EP
LT1976/LT1976B
APPLICATIO S I FOR ATIO
? 3 . 3 ? ( 125 μ A + 12 . 5 μ A + 0.. 5 μ A )
? 12 ? ?
( 0 . 8 )
V OUT
0.5V/DIV
C SS = GND
C SS = 0.1 μ F
C SS = 0.1 μ F
Example: For V OUT = 3.3V, V IN = 12V
I IN ( AVG ) = 45 μ A + 5 μ A + ?
= 45 μ A + 5 μ A + 47 μ A = 97 μ A
During the sleep portion of the Burst Mode cycle, the V C
pin voltage is held just below the level needed for normal
C OUT = 47 μ F
I LOAD = 200mA
TIME (1ms/DIV)
1976 F04
operation to improve transient response. See the Typical
Performance Characteristics section for burst and tran-
V IN = 12V
Figure 4. V OUT dV/dt
Burst Mode OPERATION (LT1976 ONLY)
To enhance efficiency at light loads, the LT1976 automati-
cally switches to Burst Mode operation which keeps the
output capacitor charged to the proper voltage while mini-
sient response waveforms.
If a no load condition can be anticipated, the supply current
can be further reduced by cycling the SHDN pin at a rate
higher than the natural no load burst frequency. Figure 6
shows Burst Mode operation with the SHDN pin. V OUT
burst ripple is maintained while the average supply current
mizing the input quiescent current. During Burst Mode
operation, the LT1976 delivers short bursts of current to
the output capacitor followed by sleep periods where the
output power is delivered to the load by the output capaci-
tor. In addition, V IN and BIAS quiescent currents are re-
duced to typically 45 μ A and 125 μ A respectively during the
sleep time. As the load current decreases towards a no
load condition, the percentage of time that the LT1976
operates in sleep mode increases and the average input
150
125
100
75
50
25
V OUT = 3.3V
T A = 25 ° C
current is greatly reduced resulting in higher efficiency.
0
The minimum average input current depends on the V IN to
V OUT ratio, V C frequency compensation, feedback divider
0
10
20 30 40
INPUT VOLTAGE (V)
50
60
1976 F05
? V ? ( I BIASS + I FB + I S )
( η )
I IN ( AVG ) ? I VINS + I SHDN + ? OUT ?
network and Schottky diode leakage. It can be approxi-
mated by the following equation:
? V IN ?
where
I VINS = input pin current in sleep mode
V OUT = output voltage
V IN = input voltage
I BIASS = BIAS pin current in sleep mode
V OUT
50mV/DIV
V SHDN
2V/DIV
I SW
Figure 5. I Q vs V IN
I FB = feedback network current
I S = catch diode reverse leakage at V OUT
500mA/DIV
V IN = 12V
V OUT = 3.3V
I Q = 15 μ A
TIME (50ms/DIV)
1976 G16
η = low current efficiency (non Burst Mode operation)
Figure 6. Burst Mode with Shutdown Pin
1976bfg
18
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