参数资料
型号: LT3023EDD
厂商: Linear Technology
文件页数: 11/16页
文件大小: 0K
描述: IC REG LDO ADJ .1A 10-DFN
产品培训模块: More Information on LDOs
标准包装: 121
稳压器拓扑结构: 正,可调式
输出电压: 1.22 V ~ 20 V
输入电压: 1.8 V ~ 20 V
电压 - 压降(标准): 0.3V @ 100mA
稳压器数量: 2
电流 - 输出: 100mA
电流 - 限制(最小): 110mA
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
供应商设备封装: 10-DFN(3x3)
包装: 管件
产品目录页面: 1330 (CN2011-ZH PDF)
LT3023
APPLICATIONS INFORMATION
case size increases, but expected capacitance at operating
voltage should be veri?ed.
Voltage and temperature coef?cients are not the only
sources of problems. Some ceramic capacitors have a
piezoelectric response. A piezoelectric device generates
voltage across its terminals due to mechanical stress,
similar to the way a piezoelectric accelerometer or micro-
phone works. For a ceramic capacitor the stress can be
induced by vibrations in the system or thermal transients.
The resulting voltages produced can cause appreciable
amounts of noise, especially when a ceramic capacitor is
used for noise bypassing. A ceramic capacitor produced
Figure 5’s trace in response to light tapping from a pencil.
Similar vibration induced behavior can masquerade as
C OUT = 10μF
C BYP = 0.01μF
Characteristics section. Power dissipation will be equal
to the sum of the two components listed above. Power
dissipation from both channels must be considered during
thermal analysis.
The LT3023 regulator has internal thermal limiting de-
signed to protect the device during overload conditions.
For continuous normal conditions, the maximum junction
temperature rating of 125°C must not be exceeded. It is
important to give careful consideration to all sources of
thermal resistance from junction to ambient. Additional
heat sources mounted nearby must also be considered.
For surface mount devices, heat sinking is accomplished
by using the heat spreading capabilities of the PC board
and its copper traces. Copper board stiffeners and plated
through-holes can also be used to spread the heat gener-
ated by power devices.
I LOAD = 100mA
The following tables list thermal resistance for several
different board sizes and copper areas. All measurements
V OUT
500μV/DIV
were taken in still air on 3/32" FR-4 board with one ounce
copper.
Table 1. MSE Package, 10-Lead MSOP
COPPER AREA
THERMAL RESISTANCE
100ms/DIV
3023 F05
TOPSIDE*
BACKSIDE
BOARD AREA (JUNCTION-TO-AMBIENT)
Figure 5. Noise Resulting from Tapping on a Ceramic Capacitor
increased output voltage noise.
2500mm 2
1000mm 2
225mm 2
2500mm 2
2500mm 2
2500mm 2
2500mm 2
2500mm 2
2500mm 2
40°C/W
45°C/W
50°C/W
Thermal Considerations
100mm 2 2500mm 2
*Device is mounted on topside.
2500mm 2
62°C/W
THERMAL RESISTANCE
The power handling capability of the device will be limited
by the maximum rated junction temperature (125°C). The
power dissipated by the device will be made up of two
components (for each channel):
Table 2. DD Package, 10-Lead DFN
COPPER AREA
TOPSIDE* BACKSIDE BOARD AREA (JUNCTION-TO-AMBIENT)
2500mm 2 2500mm 2 2500mm 2 40°C/W
1. Output current multiplied by the input/output voltage
differential: (I OUT )(V IN – V OUT ), and
2. GND pin current multiplied by the input voltage:
1000mm 2
225mm 2
100mm 2
2500mm 2
2500mm 2
2500mm 2
2500mm 2
2500mm 2
2500mm 2
45°C/W
50°C/W
62°C/W
(I GND )(V IN ).
The ground pin current can be found by examining the
GND Pin Current curves in the Typical Performance
*Device is mounted on topside.
The thermal resistance juncton-to-case ( θ JC ), measured
at the Exposed Pad on the back of the die is 10°C/W.
3023fa
11
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