参数资料
| 型号： | LT3050MPMSE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 16/26页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ .1A 12MSOP |
| 产品培训模块： | LT3050 - 100mA, Low Noise Linear Regulator With Precision Current Limit And Diagnostic Functions |
| 标准包装： | 37 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 0.6 V ~ 44.5 V |
| 输入电压： | 1.6 V ~ 45 V |
| 电压 - 压降（标准）： | 0.34V @ 100mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 100mA |
| 电流 - 限制（最小）： | 110mA |
| 工作温度： | -55°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 12-TSSOP （0.118"，3.00mm 宽）裸露焊盘 |
| 供应商设备封装： | 12-MSOP，裸露焊盘 |
| 包装： | 管件 |
LT3050 Series
OPERATION
External Programmable Current Limit (I MAX Pin)
The I MAX pin is the collector of a PNP which mirrors the
LT3050 output at a ratio of approximately 1:200 (see Block
Diagram). The I MAX pin is also the input to the precision
current limit ampli?er. If the output load increases to the
point where it causes the I MAX pin voltage to reach 0.6V,
the current limit ampli?er takes control of output regula-
tion so that the I MAX pin clamps at 0.6V, regardless of the
output voltage. The current limit threshold (I LIMIT ) is set
by attaching a resistor (R IMAX ) from I MAX to GND:
119.22 ? 0.894 ? V OUT
R IMAX =
I LIMIT
This equation is empirically derived and partially compen-
sates for early voltage effects in the I MAX current mirror.
It is valid for an input voltage range from 0.6V above the
output to 10V above the output. It is valid for output volt-
ages up to 12V. The accuracy of this equation for setting
the resistor value is approximately ±1%. Unit values are
Amps, Volts, and Ohms.
In cases where the IN to OUT voltage exceeds 10V, fold-
back current limit will lower the internal current level limit,
possibly causing it to preempt the external programmable
current limit. See the Internal Current Limit vs V IN – V OUT
graph in the Typical Performance Characteristics section.
If the external programmable current limit is not needed,
the I MAX pin must be connected to GND. The I MAX pin
requires a 10nF decoupling capacitor.
See the Typical Performance Characteristics section for
additional information.
FAULT Pin Operation
The FAULT pin is an open collector logic pin which asserts
during internal current limit, precision current limit, ther-
mal limit, or a minimum current fault. There is no internal
pull-up on the FAULT pin; an external pull-up resistor is
required. The FAULT pin provides drive for up to 100μA
of pull-down current. Off state logic may be as high as
45V, regardless of the input voltage used. When asserted,
the FAULT pin drive circuitry adds 50μA (nominal) of GND
pin current.
Depending on the I MIN capacitance, BYP capacitance,
and OUT capacitance, the FAULT pin may assert during
startup. Consideration should be given to masking the
FAULT signal during startup. The FAULT pin circuitry is
inactive (not asserted) during shutdown and when the
OUT pin is pulled above the IN pin.
Operation in Dropout
The LT3050 contains circuitry which prevents the PNP
output power device from saturating in dropout. This also
keeps the I MON , I MIN , and I MAX current mirrors functioning
accurately, even in dropout. However, this anti-saturation
circuitry becomes less active at lower output currents, so
there is some degradation of current mirror function for
output currents less than 10mA.
3050fa
16
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