参数资料
| 型号： | LT3082IDD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO ADJ .2A 8DFN |
| 标准包装： | 121 |
| 稳压器拓扑结构： | 正，可调式 |
| 输出电压： | 可调 |
| 输入电压： | 1.2 V ~ 40 V |
| 电压 - 压降（标准）： | 1.3V @ 200mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 200mA（最小值） |
| 电流 - 限制（最小）： | 200mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 供应商设备封装： | 8-DFN-EP（3x3） |
| 包装： | 管件 |
LT3082
APPLICATIONS INFORMATION
Table 1. 1% Resistors for Common Output Voltages
If guard ring techniques are used, this bootstraps any
V OUT (V)
1
1.2
1.5
1.8
2.5
3.3
5
R SET (k)
100
121
150
182
249
332
499
stray capacitance at the SET pin. Since the SET pin is
a high impedance node, unwanted signals may couple
into the SET pin and cause erratic behavior. This will
be most noticeable when operating with minimum
output capacitors at full load current. The easiest way
to remedy this is to bypass the SET pin with a small
amount of capacitance from SET to ground; 10pF to
20pF is suf?cient.
With a 10μA current source generating the reference
voltage, leakage paths to or from the SET pin can create
errors in the reference and output voltages. High qual-
ity insulation should be used (e.g., Te?on, Kel-F). The
cleaning of all insulating surfaces to remove ?uxes and
other residues may be required. Surface coating may be
necessary to provide a moisture barrier in high humidity
environments.
Minimize board leakage by encircling the SET pin and
circuitry with a guard ring that is operated at a potential
close to itself. Tie the guard ring to the OUT pin. Guarding
both sides of the circuit board is required. Bulk leakage
reduction depends on the guard ring width. 10nA of leak-
age into or out of the SET pin and its associated circuitry
creates a 0.1% reference voltage error. Leakages of this
magnitude, coupled with other sources of leakage, can
cause signi?cant offset voltage and reference drift, es-
pecially over the possible operating temperature range.
Figure 2 depicts an example guard ring layout.
Stability and Output Capacitance
The LT3082 requires an output capacitor for stability. It
is designed to be stable with most low ESR capacitors
(typically ceramic, tantalum or low ESR electrolytic). A
minimum output capacitor of 2.2μF with an ESR of 0.5Ω
or less is recommended to prevent oscillations. Larger
values of output capacitance decrease peak deviations
and provide improved transient response for larger load
current changes. Bypass capacitors, used to decouple
individual components powered by the LT3082, increase
the effective output capacitor value. For improvement in
transient response performance, place a capacitor across
the voltage setting resistor. Capacitors up to 1μF can be
used. This bypass capacitor reduces system noise as well,
but start-up time is proportional to the time constant of
the voltage setting resistor (R SET in Figure 1) and SET pin
bypass capacitor.
Give extra consideration to the use of ceramic capacitors.
Ceramic capacitors are manufactured with a variety of di-
OUT
SET
GND
3082 F02
Figure 2. Example Guard Ring Layout for DFN Package
3082f
9
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT3082IDDTR | 制造商:LINER 制造商全称:Linear Technology 功能描述:200mA Single Resistor Low Dropout Linear Regulator |
| LT3082IDDTRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:200mA Single Resistor Low Dropout Linear Regulator |
| LT3082IST | 制造商:LINER 制造商全称:Linear Technology 功能描述:200mA Single Resistor Low Dropout Linear Regulator |
| LT3082IST#PBF | 功能描述:IC REG LDO ADJ .2A SOT223-3 RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 线性 系列:- 产品培训模块:MIC5365/66 Ultra-small LDO Regulators 标准包装:1 系列:- 稳压器拓扑结构:正，固定式 输出电压:3V 输入电压:最高 5.5V 电压 - 压降（标准）:0.155V @ 150mA 稳压器数量:1 电流 - 输出:150mA 电流 - 限制（最小）:200mA 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:4-UDFN 裸露焊盘，4-TMLF? 供应商设备封装:4-TMLF?（1x1） 包装:Digi-Reel® 其它名称:576-3192-6 |
| LT3082IST#PBF | 制造商:Linear Technology 功能描述:LDO ADJ 200mA SOT-223-3 制造商:Linear Technology 功能描述:LDO, ADJ, 200mA, SOT-223-3 |
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