参数资料
型号: LT3430IFE-1#PBF
厂商: Linear Technology
文件页数: 24/28页
文件大小: 0K
描述: IC REG BUCK ADJ 3A 16TSSOP
标准包装: 95
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.2 V ~ 54 V
输入电压: 5.5 V ~ 60 V
PWM 型: 电流模式
频率 - 开关: 100kHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-TSSOP-EP
产品目录页面: 1331 (CN2011-ZH PDF)
LT3430/LT3430-1
APPLICATIONS INFORMATION
? I P – 2 ( V + V ? ( V OUT )( V IN – 0 . 15 )
? OUT IN )( f )( L ) ?
+ V – 0 . 15 )( V
+ V
DUAL OUTPUT SEPIC CONVERTER
The circuit in Figure 14 generates both positive and negative
5V outputs with a single piece of magnetics. The two induc-
tors shown are actually just two windings on a standard
Coiltronics inductor. The topology for the 5V output is a
standard buck converter. The – 5V topology would be a
simple ?yback winding coupled to the buck converter if
C4 were not present. C4 creates a SEPIC (single-ended
primary inductance converter) topology which improves
regulation and reduces ripple current in L1. Without C4,
the voltage swing on L1B compared to L1A would vary
due to relative loading and coupling losses. C4 provides a
low impedance path to maintain an equal voltage swing in
L1B, improving regulation. In a ?yback converter, during
switch on time, all the converter’s energy is stored in L1A
only, since no current ?ows in L1B. At switch off, energy
is transferred by magnetic coupling into L1B, powering
the –5V rail. C4 pulls L1B positive during switch on time,
causing current to ?ow, and energy to build in L1B and
C4. At switch off, the energy stored in both L1B and C4
supply the –5V rail. This reduces the current in L1A and
changes L1B current waveform from square to triangular.
For details on this circuit, including maximum output cur-
POSITIVE-TO-NEGATIVE CONVERTER
The circuit in Figure 15 is a positive-to-negative topology
using a grounded inductor. It differs from the standard
approach in the way the IC chip derives its feedback
signal because the LT3430/LT3430-1 accepts only posi-
tive feedback signals. The ground pin must be tied to the
regulated negative output. A resistor divider to the FB pin
then provides the proper feedback voltage for the chip.
The following equation can be used to calculate maximum
load current for the positive-to-negative converter:
? ( V IN )( V OUT ) ?
I MAX =
( V OUT IN OUT F )
I P = Maximum rated switch current
V IN = Minimum input voltage
V OUT = Output voltage
V F = Catch diode forward voltage
0.15 = Switch voltage drop at 3A
Example: with V IN(MIN) = 5.5V, V OUT = 12V, L = 10μH,
V F = 0.52V, I P = 3A: I MAX = 0.6A.
rents, see Design Note 100.
D2
MMSD914TI
C2
0.68 μ F
V IN
7.5V TO 60V
V IN
BOOST
LT3430
SW
L1A*
25 μ H
V OUT
5V
C3
4.7 μ F
100V
CERAMIC
SHDN
SYNC
GND
FB
V C
R1
15.4k
R2
4.99k
+
C1
100 μ F
10V TANT
GND
R C
3.3k
C C
0.022 μ F
C F
220pF
D1
IF LOAD CAN GO TO ZERO, AN OPTIONAL
* L1 IS A SINGLE CORE WITH TWO WINDINGS
COILTRONICS #CTX25-4A
?
PRELOAD OF 1k TO 5k MAY BE USED TO
IMPROVE LOAD REGULATION
D1, D3: 30BQ060
C4
100 μ F
10V
TANT
+
L1B*
D3
C5
100 μ F
10V TANT
+
3430 F14
V OUT
–5V ?
Figure 14. Dual Output SEPIC Converter
34301fa
24
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