参数资料
型号: LT3434EFE
厂商: Linear Technology
文件页数: 20/24页
文件大小: 0K
描述: IC REG BUCK ADJ 3A 16TSSOP
标准包装: 95
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.25 V ~ 54 V
输入电压: 3.3 V ~ 60 V
PWM 型: 电流模式,混合
频率 - 开关: 200kHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
供应商设备封装: 16-TSSOP-EP
LT3434
APPLICATIO S I FOR ATIO
4 V IN
LT3434
SW 2
L1
V OUT
Board layout also has a significant effect on thermal
resistance. Pin 8 and the exposed die pad, Pin 17, are a
+
V IN
C2
HIGH
FREQUENCY
CIRCULATION
PATH
D1
C1
LOAD
continuous copper plate that runs under the LT3434 die.
This is the best thermal path for heat out of the package.
Reducing the thermal resistance from Pin 8 and exposed
pad onto the board will reduce die temperature and in-
3434 F11
Figure 11. High Speed Switching Path
crease the power capability of the LT3434. This is achieved
by providing as much copper area as possible around the
exposed pad. Adding multiple solder filled feedthroughs
V OUT
C2
D2
CONNECT PIN 8 GND TO THE
PIN 17 EXPOSED PAD GND
under and around this pad to an internal ground plane will
also help. Similar treatment to the catch diode and coil
C1
L1
D1
PLACE VIA's UNDER EXPOSED
PAD TO A BOTTOM PLANE TO
ENHANCE THERMAL
CONDUCTIVITY
KELVIN SENSE
FEEDBACK
TRACE AND
terminations will reduce any additional heating effects.
GND
C3
MINIMIZE
D1-C3
LOOP
V IN
1 NC
2 SW
3 V IN
4 V IN
5 SW
PGOOD 16
SHDN 15
LT3434
SYNC 14
PGFB 13
FB 12
KEEP SEPARATE
FROM BIAS TRACE
R3
R1
R2
THERMAL CALCULATIONS
Power dissipation in the LT3434 chip comes from four
sources: switch DC loss, switch AC loss, boost circuit
current, and input quiescent current. The following formu-
las show how to calculate each of these losses. These
C4
6 BOOST
7 C T
8 GND
V C 11
BIAS 10
C SS 9
C5
C2
formulas assume continuous mode operation, so they
should not be used for calculating efficiency at light load
currents.
Switch loss:
R SW ( I OUT ) ( V OUT )
GND
Figure 12. Suggested Layout
3434 F12
P SW
=
2
V IN
+ t EFF ( 1 / 2 )( I OUT )( V IN )( f )
Boost current loss:
LT3434 switch. When operating at higher currents and
input voltages, with poor layout, this spike can generate
voltages across the LT3434 that may exceed its absolute
P BOOST
=
( V OUT ) ( 2 I OUT /40 )
V IN
maximum rating. A ground plane should always be used
under the switcher circuitry to prevent interplane coupling
and overall noise.
The V C and FB components should be kept as far away as
possible from the switch and boost nodes. The LT3434
pinout has been designed to aid in this. The ground for
these components should be separated from the switch
current path. Failure to do so will result in poor stability or
subharmonic like oscillation.
Quiescent current loss:
P Q = V IN (0.0026) + V OUT (0.001)
R SW = switch resistance ( ≈ 0.15 when hot )
t EFF = effective switch current/voltage overlap time
(t r + t f + t IR + t IF )
t r = (V IN /1.2)ns
t f = (V IN /1.7)ns
t IR = t IF = (I OUT /0.2)ns
f = switch frequency
3434fb
20
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