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| 型号： | LT3437IDD#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 19/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 0.5A 10DFN |
| 标准包装： | 121 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.25 V ~ 54 V |
| 输入电压： | 3.3 V ~ 60 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 200kHz |
| 电流 - 输出： | 500mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 10-DFN（3x3） |
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LT3437
APPLICATIO S I FOR ATIO
SHUTDOWN FUNCTION AND UNDERVOLTAGE
LT3437
LOCKOUT
The SHDN pin on the LT3437 controls the operation of the
IC. When the voltage on the SHDN pin is below the 1.3V
shutdown threshold, the LT3437 is placed in a “zero”
supply current state. Driving the SHDN pin above the
shutdown threshold enables normal operation. The SHDN
pin has an internal sink current with a typical value of 5 μ A.
In addition to the shutdown feature, the LT3437 has an
V OUT
R3
R1
R2
2
10
V IN
SHDN
5 μ A
2.5V
1.3V
+
V IN
COMP
–
+
SHDN
COMP
–
ENABLE
undervoltage lockout function. When the input voltage is
V UVLO = R 1 ? SHDN + + I SHDN ? + V SHDN
V OUT ( R 1 )
R 1 =
( ) . 1 5 ( I SHDN ( TYP ) )
below 2.5V, switching will be disabled. The undervoltage
lockout threshold doesn’t have any hysteresis and is
mainly used to insure that all internal voltages are at the
correct level before switching is enabled. If an undervolt-
age lockout function with hysteresis is needed to limit
input current at low V IN to V OUT ratios, refer to Figure 7 and
the following:
? V V SHDN ?
? R 3 R 2 ?
V HYST =
R 3
R1 should be chosen to minimize quiescent current during
normal operation by the following equation:
V IN – 2 V
Example:
3437 F07
Figure 7. Undervoltage Lockout
SYNCHRONIZING
Oscillator synchronization to an external input is achieved
by connecting a TTL logic-compatible square wave with a
duty cycle between 25% and 75% to the LT3437 SYNC
pin. The synchronizing range is equal to initial operating
frequency up to 700kHz. This means that minimum
practical sync frequency is equal to the worst-case high
self-oscillating frequency (240kHz), not the typical oper-
ating frequency of 200kHz. Caution should be used when
synchronizing above 300kHz, because at higher sync
frequencies the amplitude of the internal slope compen-
sation used to prevent subharmonic switching is re-
duced. This type of subharmonic switching only occurs at
input voltages less than twice output voltage. Higher
inductor values will tend to eliminate this problem. See
Frequency Compensation section for a discussion of an
R 1 =
R 3 =
12 – 2
1 . 5 ( 5 μ A )
5 ( 1 . 3 M ?
1
= 1 . 3 M ?
) = 6 . 5 M ? (Nearest 1% 6.49M ? )
entirely different cause of subharmonic switching before
assuming that the cause is insufficient slope compensa-
tion. Application Note 19 has more details on the theory
of slope compensation.
If the FB pin voltage is below 0.9V (power-up or output
short-circuit conditions), the sync function is disabled.
– 1 μ A –
1.3
R2 =
7 – 1.3 1 . 3
1.3M ? 6 . 49 M ?
= 408 k (Nearest 1% 412k)
See the Typical Performance Characteristics section for
graphs of SHDN and V IN currents verses input voltage.
This allows the frequency foldback to operate to avoid
hazardous conditions for the SW pin.
If a synchronization signal or logic-level above 2V is
present at the SYNC pin, Burst Mode operation is disabled.
Burst Mode operation can be enabled or disabled on the
fly. If no synchronization or Burst Mode defeat is required,
this pin should be connected to ground.
3437fc
19
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