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参数资料
| 型号： | LT3437IDD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 0.5A 10DFN |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1.25 V ~ 54 V |
| 输入电压： | 3.3 V ~ 60 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 200kHz |
| 电流 - 输出： | 500mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-DFN（3x3） |
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LT3437
PI FU CTIO S
(DD/FE)
SW (Pin 1/Pin 2): The SW pin is the emitter of the on-chip
power NPN switch. This pin is driven up to the input pin
voltage during switch on time. Inductor current drives the
SW pin negative during switch off time. Negative voltage
is clamped with an external schottky catch diode to pre-
vent excessive negative voltages.
NC (Pins 1, 3, 5, 7, 13, 16)(FE Package ONLY):
No Connection. The NC pins are electrically isolated from
the LT3437. The NC pins may be connected to PCB traces
to aid PCB layout.
V IN (Pin 2/Pin 4): This is the collector of the on-chip power
NPN switch. V IN powers the internal control circuitry when
a voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the V IN pin through the input bypass
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the V CE voltage across the internal NPN.
BOOST (Pin 3/Pin 6): The BOOST pin is used to provide a
drive voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.8 ? FET
structure.
GND (Pins 4, 11/Pins 8, 17): The GND pin connection
acts as the reference for the regulated output, so load
regulation will suffer if the “ground” end of the load is not
at the same voltage as the GND pin of the IC. This
condition will occur when load current or other currents
flow through metal paths between the GND pin and the
load ground. Keep the path between the GND pin and the
load ground short and use a ground plane when possible.
The GND pin also acts as a heat sink and should be
soldered (along with the exposed leadframe) to the cop-
per ground plane to reduce thermal resistance (see Appli-
cations Information).
C SS (Pin 5/Pin 9): A capacitor from the C SS pin to the
regulated output voltage determines the output voltage
ramp rate during start-up. When the current through the
C SS capacitor exceeds the C SS threshold (I CSS ), the volt-
age ramp of the output is limited. The C SS threshold is
proportional to the FB voltage (see Typical Performance
Characteristics) and is defeated for FB voltage greater than
0.9V (typical). See Soft-Start section in Applications Infor-
mation for details.
3437fc
8
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