参数资料
型号: LT3470EDDB#TRMPBF
厂商: Linear Technology
文件页数: 13/20页
文件大小: 0K
描述: IC REG BUCK ADJ 0.2A 8DFN
标准包装: 500
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.25 V ~ 16 V
输入电压: 4 V ~ 40 V
PWM 型: Burst Mode?
电流 - 输出: 200mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 8-DFN(3x2)
LT3470
APPLICATIONS INFORMATION
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Note that large,
switched currents flow in the power switch, the internal
catch diode and the input capacitor. The loop formed by
these components should be as small as possible. Further-
more, the system ground should be tied to the regulator
ground in only one place; this prevents the switched cur-
rent from injecting noise into the system ground. These
components, along with the inductor and output capacitor,
should be placed on the same side of the circuit board,
and their connections should be made on that layer. Place
a local, unbroken ground plane below these components,
and tie this ground plane to system ground at one location,
SHDN
ideally at the ground terminal of the output capacitor C2.
Additionally, the SW and BOOST nodes should be kept as
small as possible. Unshielded inductors can induce noise
in the feedback path resulting in instability and increased
output ripple. To avoid this problem, use vias to route the
V OUT trace under the ground plane to the feedback divider
(as shown in Figure 5). Finally, keep the FB node as small
as possible so that the ground pin and ground traces
will shield it from the SW and BOOST nodes. Figure 5
shows component placement with trace, ground plane
and via locations. Include vias near the GND pin, or pad,
of the LT3470 to help remove heat from the LT3470 to
the ground plane.
SHDN
V IN
GND
C1
V IN
GND
VIAS TO FEEDBACK DIVIDER
VIAS TO LOCAL GROUND PLANE
C2
V OUT
V OUT
3470 F05
OUTLINE OF LOCAL GROUND PLANE
(5a)
(5b)
Figure 5. A Good PCB Layout Ensures Proper, Low EMI Operation
3470fd
13
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