参数资料
型号: LT3472EDD#TR
厂商: Linear Technology
文件页数: 8/12页
文件大小: 0K
描述: IC REG BOOST INV ADJ 50MA 10DFN
标准包装: 2,500
类型: 升压(升压),反相
输出类型: 可调式
输出数: 1
输出电压: 可调至 ±34V
输入电压: 2.2 V ~ 16 V
PWM 型: 电流模式
频率 - 开关: 1.1MHz
电流 - 输出: 50mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 10-DFN(3x3)
LT3472
APPLICATIO S I FOR ATIO
and larger capacitance, which can cause significant switch-
ing losses at 1.1MHz switching frequency. Some recom-
In order to maintain accuracy, high precision resistors are
preferred (1% is recommended).
mended Schottky diodes are listed in Table 4.
Soft-Start
Table 4. Recommended Schottky Diodes
Forward Forward Diode
Current Voltage Capacitance
Part No. (mA) Drop (V) (pF) Manufacturer
The LT3472 has independent soft-start control for each
channel. As shown in Figure 1, the SSP and SSN pins have
an internal resistor of 50k pulling up to 1.25V, respec-
CMDSH-3
CMDSH2-3
100
200
0.58 @100mA 7 @ 10V
0.49 @ 200mA 15 @ 10V
Central Semiconductor
(631) 435-1110
tively. By connecting a capacitor from the SSP or SSN pin
to ground, the ramp of each output can be programmed
V POS = 1 . 25 ? ? 1 +
?
50 k ?
V NEG = – 1 . 25 ? ?
? 50 k ?
www.centralsemi.com
Setting the Output Voltages
The LT3472 has an accurate feedback resistor of 50k for
each channel. Only one resistor is needed to set the output
voltage for each channel. The output voltage can be set
according to the following formulas:
? R 1 ?
?
? R 2 ?
?
V SSP
1V/DIV
V POS
5V/DIV
I IN
100mA/DIV
individually. If SSP or SSN is open or pull higher than
1.25V, the corresponding output will ramp up quickly. The
waveforms with and without soft-start for the Boost
channel are shown in Figure 4.
The waveforms with and without soft-start for the negative
channel are shown in Figure 5.
Start Sequencing
The LT3472 has internal sequencing circuitry that inhibits
the negative channel from operating until feedback voltage
of the step-up channel reaches about 1.1V, ensuring that
V SSP
2V/DIV
V POS
5V/DIV
I IN
200mA/DIV
1ms/DIV
3472 FO4a
100 μ s/DIV
3472 FO4b
Figure 4a. V SSP , V POS , I IN with 100nF on SSP
V SSN
1V/DIV
V NEG
5V/DIV
I IN
100mA/DIV
Figure 4b. V SSP , V POS , I IN with SSP Open
V SSN
2V/DIV
V NEG
5V/DIV
I IN
200mA/DIV
500 μ s/DIV
3472 FO5a
100 μ s/DIV
3472 FO5b
Figure 5a. V SSN , V NEG , I IN with 100nF on SSN
Figure 5b. V SSN , V NEG , I IN with SSN Open
3472f
8
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