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参数资料
| 型号： | LT3473EDD#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 5/12页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST ADJ 1A 8DFN |
| 标准包装： | 2,500 |
| 类型： | 升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 34V |
| 输入电压： | 2.2 V ~ 16 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 1.2MHz |
| 电流 - 输出： | 1A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 8-DFN-EP（3x3） |
LT3473/LT3473A
TYPICAL PERFOR A CE CHARACTERISTICS T A = 25 ° C unless otherwise noted.
SHDN Voltage to Turn-On
1.4
1.2
Disconnect PNP Quiescent Current
0.9
0.8
0.7
Disconnect PNP
1.00
0.95
0.90
Auxiliary NPN V BE
1.0
0.8
0.6
0.4
0.2
0
0.6
0.5
0.4
0.3
0.2
0.1
0
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
I E = 1mA
I E = 100 μ A
0
5
10
15
20
25
30
35
40
0
20
40
60
80
100
–50
0
50
100
CAP VOLTAGE (V)
3473 G13
PI FU CTIO S (LT3473/LT3473A)
OUTPUT CURRENT (mA)
3473 G14
TEMPERATURE ( ° C)
3473 G15
CAP (Pin 1/Pin 1): Internal Output Voltage. This pin is the
Schottky cathode and disconnect PNP emitter. Connect
output capacitor here.
OUT (Pin 2/Pin 2): Output of Disconnect Circuit. Bypass
this pin with capacitor to ground.
CTRL (Pin 3/Pin 8): External Reference Pin. This pin sets
the FB voltage externally between 0V and 1.25V. Tie this
pin 1.5V or higher to use the internal 1.25V reference.
FB (Pin 4/Pin 7): Feedback Pin. Pin voltage is regulated to
1.25V if internal reference is used or to the CTRL pin
voltage if the CTRL pin voltage is between 0V and 1.25V.
Connect the feedback resistor divider to this pin. The
output voltage is regulated to:
SHDN (Pin 6/Pin 10): Shutdown Pin. Connect to 1.4V or
higher to enable device; 0.2V or less to disable device. Also
functions as soft-start. Use RC filter as shown in Figure 4.
V IN (Pin 7/Pin 11): Input Supply Pin. Must be locally
bypassed with a X5R or X7R type ceramic capacitor.
SW (Pin 8/Pin 12): Switch Pin. Connect inductor here.
Minimize the metal trace area connected to the pin to
minimize EMI.
Exposed Pad (Pin 9/Pin 13): Ground. Solder directly to
PCB ground plane through multiple vias under the pack-
age for optimum thermal performance.
LT3473A Only
NB1 (Pin 3): NPN1 Base.
V OUT = V REF ? ?
+ 1 ?
? R2
? R 1
?
?
NE1 (Pin 4): NPN1 Emitter.
NB2 (Pin 5): NPN2 Base.
PGOOD (Pin 5/Pin 9): Power Good Output. Open collector
logic output that starts to sink current when FB reaches
NE2 (Pin 6): NPN2 Emitter.
within 100mV of the reference voltage.
3473f
5
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