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LT3502/LT3502A
16
3502f
APPLICATIONS INFORMATION
voltage overshoot (it also reduces the peak input current).
A 0.1μF capacitor improves high frequency ltering. This
solution is smaller and less expensive than the electrolytic
capacitor. For high input voltages its impact on efciency
is minor, reducing efciency less than one half percent for
a 5V output at full load operating from 24V.
Frequency Compensation
The LT3502/LT3502A use current mode control to regulate
the output. This simplies loop compensation. In particular,
the LT3502/LT3502A does not require the ESR of the output
capacitor for stability allowing the use of ceramic capacitors
to achieve low output ripple and small circuit size.
Figure 10 shows an equivalent circuit for the LT3502/
LT3502A control loop. The error amp is a transconductance
amplier with nite output impedance. The power section,
consisting of the modulator, power switch and inductor,
is modeled as a transconductance amplier generating an
output current proportional to the voltage at the VC node.
Note that the output capacitor integrates this current, and
that the capacitor on the VC node (CC) integrates the er-
ror amplier output current, resulting in two poles in the
loop. RC provides a zero. With the recommended output
capacitor, the loop crossover occurs above the RCCC zero.
This simple model works well as long as the value of the
inductor is not too high and the loop crossover frequency
is much lower than the switching frequency. With a larger
ceramic capacitor (very low ESR), crossover may be lower
and a phase lead capacitor (CPL) across the feedback
divider may improve the phase margin and transient
response. Large electrolytic capacitors may have an ESR
large enough to create an additional zero, and the phase
lead may not be necessary.
If the output capacitor is different than the recommended
capacitor, stability should be checked across all operating
conditions, including load current, input voltage and tem-
perature. The LT1375 data sheet contains a more thorough
discussion of loop compensation and describes how to
test the stability using a transient load.
PCB Layout
For proper operation and minimum EMI, care must be taken
during printed circuit board layout. Figure 11 shows the
recommended component placement with trace, ground
plane and via locations. Note that large, switched currents
ow in the LT3502/LT3502A’s VIN and SW pins, the catch
diode (D1) and the input capacitor (C2). The loop formed by
these components should be as small as possible and tied
to system ground in only one place. These components,
along with the inductor and output capacitor, should be
placed on the same side of the circuit board, and their
connections should be made on that layer. Place a local,
unbroken ground plane below these components, and tie
this ground plane to system ground at one location, ideally
at the ground terminal of the output capacitor C1. The SW
and BOOST nodes should be as small as possible. Finally,
keep the FB node small so that the ground pin and ground
traces will shield it from the SW and BOOST nodes. Include
vias near the exposed GND pad of the LT3502/LT3502A
to help remove heat from the LT3502/LT3502A to the
ground plane.
Figure 11
BST
DA
GND
D1
FB
VIN
VOUT
L1
C1
C2
C3
R1
R2
= VIA
3502 F11
BD
SHDN