参数资料
型号: LT3506AEDHD#PBF
厂商: Linear Technology
文件页数: 7/24页
文件大小: 0K
描述: IC REG BUCK ADJ 1.6A DL 16DFN
标准包装: 73
类型: 降压(降压)
输出类型: 可调式
输出数: 2
输出电压: 0.8 V ~ 22 V
输入电压: 3.6 V ~ 25 V
PWM 型: 电流模式
频率 - 开关: 1.1MHz
电流 - 输出: 1.6A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-WFDFN 裸露焊盘
包装: 管件
供应商设备封装: 16-DFN(5x4)
LT3506/LT3506A
OPERATION
(Refer to the Block Diagram)
The LT3506 is a dual, constant frequency, current mode
buck regulator with internal 2A power switches. The two
regulators share common circuitry including voltage
reference and oscillator. In addition, the analog blocks
on both regulators share the V IN1 supply voltage, but are
otherwise independent. This section describes the opera-
tion of the LT3506.
If the RUN/SS (run/soft-start) pins are both tied to ground,
the LT3506 is shut down and draws 30μA from V IN1 .
Internal 2μA current sources charge external soft-start
capacitors, generating voltage ramps at these pins. If either
RUN/SS pin exceeds 0.6V, the internal bias circuits turn
on, including the internal regulator, 800mV reference and
575kHz master oscillator. In this state, the LT3506 draws
3.8mA from V IN1 , whether one or both RUN/SS pins are
high. Neither switching regulator will begin to operate
until its RUN/SS pin reaches ~0.8V. The master oscillator
generates two clock signals of opposite phase.
The two switchers are current mode, step-down regulators.
This means that instead of directly modulating the duty
cycle of the power switch, the feedback loop controls the
peak current in the switch during each cycle. This cur-
rent mode control improves loop dynamics and provides
cycle-by-cycle current limit.
The Block Diagram in Figure 2 shows only one of the two
switching regulators. A pulse from the slave oscillator
sets the RS ?ip-?op and turns on the internal NPN bipolar
power switch. Current in the switch and the external induc-
tor begins to increase. When this current exceeds a level
determined by the voltage at V C , current comparator C1
resets the ?ip-?op, turning off the switch. The current in
the inductor ?ows through the external Schottky diode,
and begins to decrease. The cycle begins again at the next
pulse from the oscillator. In this way the voltage on the V C
pin controls the current through the inductor to the output.
The internal error ampli?er regulates the output voltage
by continually adjusting the V C pin voltage.
The threshold for switching on the V C pin is 0.75V, and an
active clamp of 1.9V limits the output current. The V C pin
is also clamped to the RUN/SS pin voltage. As the internal
current source charges the external soft-start capacitor,
the current limit increases slowly. Each switcher contains
an independent oscillator. This slave oscillator is normally
synchronized to the master oscillator. However, during
start-up, short-circuit or overload conditions, the FB pin
voltage will be near zero and an internal comparator gates
the master oscillator clock signal. This allows the slave
oscillator to run the regulator at a lower frequency. This
frequency foldback behavior helps to limit switch current
and power dissipation under fault conditions.
The switch driver operates from either the input or from
the BOOST pin. An external capacitor and diode are used
to generate a voltage at the BOOST pin that is higher than
the input supply. This allows the driver to fully saturate
the internal bipolar NPN power switch for ef?cient opera-
tion.
A power good comparator trips when the FB pin is at 90%
of its regulated value. The PG output is an open collector
transistor that is off when the output is in regulation, al-
lowing an external resistor to pull the PG pin high. Power
good is valid when the LT3506 is enabled (either RUN/SS
pin is high) and V IN is greater than ~3.4V.
3506afc
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