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| 型号： | LT3512MPMS#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 12/26页 |
| 文件大小： | 0K |
| 描述： | IC REG FLYBK ISO ADJ .42A 16MSOP |
| 标准包装： | 37 |
| 类型： | 回扫，隔离 |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调 |
| 输入电压： | 4.5 V ~ 100 V |
| PWM 型： | 电流模式，混合 |
| 频率 - 开关： | 40kHz ~ 650kHz |
| 电流 - 输出： | 420mA |
| 同步整流器： | 无 |
| 工作温度： | -55°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TFSOP（0.118"，3.00mm），12 引线 |
| 包装： | 管件 |
| 供应商设备封装： | 16-MSOP |
LT3512
APPLICATIONS INFORMATION
during that time, oscillation may occur at the output as
the current control loop will lose its ability to regulate. The
following equation based on maximum input voltage must
also be followed in selecting primary-side magnetizing
inductance:
V SW
<150V
<100V
V LEAKAGE
L PRI ≥
t ON(MIN) ? V IN(MAX)
I PEAK(MIN)
t OFF > 400ns
t ON(MIN) = 100ns
t SP < 150ns
TIME
t SP < 150ns
I PEAK(MIN) =100mA
Leakage Inductance and Clamp Circuits
Transformer leakage inductance (on either the primary or
secondary) causes a voltage spike to appear at the primary
after the output switch turns off. This spike is increasingly
prominent at higher load currents where more stored en-
ergy must be dissipated. When designing an application,
adequate margin should be kept for the effect of leakage
voltage spikes. In most cases the reflected output voltage
on the primary plus V IN should be kept below 100V. This
leaves at least 50V of margin for the leakage spike across
line and load conditions. A larger voltage margin will be
needed for poorly wound transformers or for excessive
leakage inductance. Figure 5 illustrates this point. Minimize
transformer leakage inductance.
A clamp circuit is recommended for most applications.
Two circuits that can protect the internal power switch
include the RCD (resistor-capacitor-diode) clamp and the
DZ (diode-Zener) clamp. The clamp circuits dissipate the
stored energy in the leakage inductance. The DZ clamp
is the recommended clamp for the LT3512. Simplicity of
design, high clamp voltages, and low power levels make the
DZ clamp the preferred solution. Additionally, a DZ clamp
ensures well defined and consistent clamping voltages.
Figure 5 shows the clamp effect on the switch waveform
and Figure 6 shows the connection of the DZ clamp.
Proper care must be taken when choosing both the diode
and the Zener diode. Schottky diodes are typically the best
choice, but some PN diodes can be used if they turn on
fast enough to limit the leakage inductance spike. Choose
a diode that has a reverse-voltage rating higher than the
maximum switch voltage. The Zener diode breakdown
voltage should be chosen to balance power loss and switch
without Clamp
V SW
<150V
<140V
<100V
t OFF > 400ns
TIME
3512 F05
with Clamp
Figure 5. Maximum Voltages for SW Pin Flyback Waveform
L S
Z
D
3512 F06
Figure 6. DZ Clamp
voltage protection. The best compromise is to choose the
largest voltage breakdown. Use the following equation to
make the proper choice:
V ZENER(MAX) ≤ 150V – V IN(MAX)
For an application with a maximum input voltage of 72V,
choose a 68V V ZENER which has V ZENER(MAX) at 72V, which
will be below the 78V maximum.
The power loss in the clamp will determine the power rat-
ing of the Zener diode. Power loss in the clamp is highest
at maximum load and minimum input voltage. The switch
3512fb
12
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