参数资料
| 型号： | LT3513IUHF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/22页 |
| 文件大小： | 0K |
| 描述： | IC REG 5-OUT FOR TFT-LCD 38QFN |
| 标准包装： | 52 |
| 应用： | 转换器，TFT，LCD |
| 输入电压： | 4.5 V ~ 30 V |
| 输出数： | 5 |
| 输出电压： | 0.8 V ~ 40 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-WFQFN 裸露焊盘 |
| 供应商设备封装： | 38-QFN（5x7） |
| 包装： | 管件 |
| 产品目录页面： | 1332 (CN2011-ZH PDF) |
LT3513
PIN FUNCTIONS
FB5 (Pin 1): Feedback Pin. Tie the resistor tap to this pin
and set the output of the LDO according to V LDO = 0.625 ?
(1 + R14/R15). Reference designators refer to Figure 1.
V C1 (Pin 2): Control Voltage and Compensation Pin for
Internal Error Amplifier. Connect a series RC from this pin
to ground to compensate switching regulator 1.
RUN-SS3/4 (Pin 3): Run/Soft-Start Pin. This is the soft-
start pin for switching regulators 3 and 4. Place a soft-start
capacitor here to limit start-up inrush current and output
voltage ramp rate. When the BIAS pin reaches 2.25V, a 2μA
current source charges the capacitor. When the voltage at
this pin reaches 0.8V, switches 3 and 4 turn on and begin
switching. For slower start-up use a larger capacitor. For
complete shutdown tie RUN-SS3/4 to ground.
FB3 (Pin 4): Feedback Pin. Tie the resistor tap to this pin
and set V ON according to V ON = 1.22V ? (1 + R8/R9) –
150mV. Reference designators refer to Figure 1.
RUN-SS2 (Pin 5): Run/Soft-Start Pin. This is the soft-start
pin for switching regulator 2. Place a soft-start capacitor
here to limit start-up inrush current and output voltage
ramp rate. When the BIAS pin reaches 2.25V, a 2μA cur-
rent source charges the capacitor. When the voltage at this
pin reaches 0.8V, switch 2 turns on and begins switching.
For slower start-up use a larger capacitor. For complete
shutdown tie RUN-SS2 to ground.
SW3 (Pin 6): Switch Node. The SW3 pin is the collector of
the internal NPN bipolar transistor for switching regulator 3.
Minimize trace area at this pin to keep EMI down.
E3 (Pin 7): This is switching regulator 3’s output and
the emitter of the output disconnect PNP. Tie the output
capacitor and resistor divider here.
V ON (Pin 8): This is the delayed output for switching
regulator 3. V ON reaches its programmed voltage after the
internal C T timer times out. Protection circuitry ensures
V ON is disabled if any of the four outputs are more than
10% below normal voltage. This output is also disabled
when V ON_CLK is high.
V ONSINK (Pin 9): This is an open-collector output controlled
by the V ON_CLK pin. When V ON_CLK is low, this pin draws no
current and when V ON_CLK is high, this pin draws current.
V ON_CLK (Pin 10): This pin controls the output disconnect
device and the open collector of V ONSINK . When this pin is
low, the V ON pin is enabled and the V ONSINK pin is a high
impedance. When this pin is high, the V ON pin is disabled
and the V ONSINK pin sinks current to ground.
PGOOD (Pin 11): Power Good Comparator Output. This is
the open collector output of the power good comparator
and can be used in conjunction with an external P-channel
MOSFET to provide output disconnect for AV DD as shown in
Figure 2. When switcher 2’s output reaches approximately
90% of its programmed voltage, PGOOD will be pulled to
ground. This will pull down on the gate of the MOSFET,
connecting AV DD . A 100k pull-up resistor between the
source and the gate of the P-channel MOSFET keeps it
off when switcher 2’s output is low.
V C3 (Pin 12): Control Voltage and Compensation Pin for
Internal Error Amplifier. Connect a series RC from this pin
to ground to compensate switching regulator 3.
C T (Pin 13): Timing Capacitor Pin. This is the input to
the V ON timer and programs the time delay from all four
feedback pins reaching 1.125V to V ON turning on. The C T
capacitor value can be set using the equation C = (20μA
? t DELAY )/1.1V.
GND (Pins 14, 17, 33): Ground.
SW2 (Pins 15, 16): Switch Node. The SW2 pin is the col-
lector of the internal NPN bipolar transistor for switching
regulator 2. Minimize trace area at this pin to keep EMI
down.
BIAS (Pins 18, 29): The BIAS pin is used to improve effi-
ciency when operating at higher input voltages. Connecting
this pin to the output of switching regulator 1 forces most
of the internal circuitry to draw its operating current from
V LOGIC rather than V IN . The drivers of switches 2, 3 and
4 and the LDO are supplied by BIAS. Switches 2, 3 and 4
and the LDO will not function until the BIAS pin reaches
approximately 2.7V. Both BIAS pins must be tied to V LOGIC .
FB2 (Pin 19): Feedback Pin. Tie the resistor divider tap
to this pin and set AV DD according to AV DD = 1.22V ?
(1 + R5/R6). Reference designators refer to Figure 2.
3513fc
8
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