参数资料
型号: LT3579EFE-1#PBF
厂商: Linear Technology
文件页数: 24/40页
文件大小: 0K
描述: IC REG MULTI CONFIG SYNC 20TSSOP
标准包装: 74
类型: 升压(升压),反相,回扫,Sepic
输出数: 1
输入电压: 2.5 V ~ 16 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 2.5MHz
电流 - 输出: 6A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-TSSOP(0.173",4.40mm 宽)裸露焊盘
包装: 管件
供应商设备封装: 20-TSSOP-EP
LT3579/LT3579-1
APPENDIX
| V OUT – V FB |
R FB =
DC BOOST ?
DC SEPIC _& _INVERT ?
DC SI_INVERT ?
SETTINGTHEOUTPUTVOLTAGE
The output voltage is set by connecting a resistor (R FB )
from V OUT to the FB pin. R FB is determined from the
following equation:
83.3μA
where V FB is 1.215V (typical) for non-inverting topologies
(i.e. boost and SEPIC regulators) and 9mV (typical) for
inverting topologies (see Electrical Characteristics).
POWER SWITCH DUTY CYCLE
In order to maintain loop stability and deliver adequate
current to the load, the power NPNs (Q1 and Q2 in the
Block Diagram) cannot remain “on” for 100% of each clock
cycle. The maximum allowable duty cycle is given by:
DC MAX = ( T P – MinOffTime ) ? 100%
T P
where T P is the clock period and MinOffTime (found in the
Electrical Characteristics) is typically 45nS.
Conversely, the power NPNs (Q1 and Q2 in the Block
Diagram) cannot remain “off” for 100% of each clock
cycle, and will turn on for a minimum time (MinOnTime)
when in regulation. This MinOnTime governs the minimum
allowable duty cycle given by:
DC MIN = ( MinOnTime ) ? 100%
T P
where T P is the clock period and MinOnTime (found in the
Electrical Characteristics) is typically 55nS.
The application should be designed such that the operating
duty cycle is between DC MIN and DC MAX .
Duty cycle equations for several common topologies are
given below where V D is the diode forward voltage drop
and V CESAT is typically 250mV at 5.5A for a combined
SW1 and SW2 current.
For the boost topology (see Figure 6):
V OUT – V IN + V D
V OUT + V D – V CESAT
For the SEPIC or Dual Inductor Inverting topology (see
Figures 7 and 8):
V D + | V OUT |
V IN + | V D | + V OUT ? V CESAT
For the Single Inductor Inverting topology (see Figure 14):
| V OUT | ? V IN + V CESAT + 3 ? V D
| V OUT | + 3 ? V D
The LT3579 can be used in configurations where the duty
cycle is higher than DC MAX , but it must be operated in
the discontinuous conduction mode so that the effective
duty cycle is reduced.
INDUCTOR SELECTION
The high frequency operation of the LT3579 allows for
the use of small surface mount inductors. For high
efficiency, choose inductors with high frequency core
material, such as ferrite, to reduce core losses. Also to
improve efficiency, choose inductors with more volume
for a given inductance. The inductor should have low
DCR (copper-wire resistance) to reduce I 2 R losses, and
must be able to handle the peak inductor current without
saturating. Note that in some applications, the current
handling requirements of the inductor can be lower, such
as in the SEPIC topology where each inductor only carries
one half of the total switch current. Multilayer chokes or
chip inductors usually do not have enough core volume to
support peak inductor currents in the 4A to 7A range. To
minimize radiated noise, use a toroidal or shielded inductor.
See Table 5 for a list of inductor manufacturers.
35791f
24
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