参数资料
型号: LT3579EUFD#TRPBF
厂商: Linear Technology
文件页数: 16/40页
文件大小: 0K
描述: IC REG MULTI CONFIG SYNC 20QFN
标准包装: 2,500
类型: 升压(升压),反相,回扫,Sepic
输出数: 1
输入电压: 2.5 V ~ 16 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 2.5MHz
电流 - 输出: 6A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
包装: 带卷 (TR)
供应商设备封装: 20-QFN 裸露焊盘(5x4)
LT3579/LT3579-1
APPLICATIONS INFORMATION
LAYOUT GUIDELINES FOR BOOST, SEPIC, AND DUAL
INDUCTOR INVERTING TOPOLOGIES
General Layout Guidelines
? To optimize thermal performance, solder the exposed
ground pad of the LT3579 to the ground plane with
multiple vias around the pad connecting to additional
ground planes.
? A ground plane should be used under the switcher circuitry
to prevent interplane coupling and overall noise.
? High speed switching path (see specific topology below for
more information) must be kept as short as possible.
? The V C , FB, and RT components should be placed as
close to the LT3579 as possible, while being as far
away as practically possible from the switch node. The
ground for these components should be separated from
the switch current path.
? Place the bypass capacitor for the V IN pin (C VIN ) as
close as possible to the LT3579.
? Place the bypass capacitor for the inductor (C PWR ) as
close as possible to the inductor.
? Bypass capacitors, C PWR and C VIN , may be combined
into a single bypass capacitor, C IN , if the input side of the
inductor can be close to the V IN pin of the LT3579.
? The load should connect directly to the positive and
negative terminals of the output capacitor for best load
regulation.
Boost Topology Specific Layout Guidelines
? Keep length of loop (high speed switching path)
governing switch, diode D1, output capacitor C OUT , and
ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
SEPIC Topology Specific Layout Guidelines
? Keep length of loop (high speed switching path) governing
switch, flying capacitor C1, diode D1, output capacitor C OUT ,
and ground return as short as possible to minimize parasitic
inductive spikes at the switch node during switching.
VIAS TO GROUND PLANE REQUIRED TO IMPROVE
THERMAL PERFORMANCE
GND
1
2
3
4
21
20
19
18
17
SYNC
SHDN
C IN
5
6
16
15
CLKOUT
A
7
8
14
13
B
V IN
9
12
C OUT1
C OUT
10
11
V OUT
+
L1
D1
M1
+
D2
R GATE
35791 F08
A– RETURN C IN GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE C IN GROUND
WITH GND EXCEPT AT THE EXPOSED PAD.
B– RETURN C OUT AND C OUT1 GROUND DIRECTLY TO LT3579 EXPOSED PAD PIN 21. IT IS ADVISED TO NOT COMBINE
C OUT AND C OUT1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD.
16
Figure 9. Suggested Component Placement for Boost Topology in FE20 Package
35791f
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