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参数资料
| 型号： | LT3585EDDB-3#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 1.85 A BATTERY CHARGE CONTROLLER, PDSO10 |
| 封装： | 3 X 2 MM, LEAD FREE, PLASTIC, MO-229WECD-1, DFN-10 |
| 文件页数： | 14/20页 |
| 文件大小： | 423K |
| 代理商： | LT3585EDDB-3#PBF |
LT3585-0/LT3585-1
LT3585-2/LT3585-3
3
3585f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Ratings are for DC levels only.
The
● denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. VIN = VBAT = VCHRG = 3V unless otherwise noted (Note 2). Specications
are for the LT3585-0, LT3585-1, LT3585-2, LT3585-3 unless otherwise noted.
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
CHRG/IADJ Three-State Voltage for Reduced Input
Current
CHRG/IADJ > 1.1V then Float
1.1
1.28
1.4
V
CHRG/IADJ Voltage Range for Normal Input Current
●
1.6
10
V
CHRG/IADJ Low Voltage
●
0.3
V
Delay Time for Reduced Input Current Mode
CHRG/IADJ Pin Three Stated:
VBAT = 4.2V, Fresh Li-Ion Cell
VBAT = 2.8V, Dead Li-Ion Cell
VBAT = 3V, Fresh 2 AA Cells
VBAT = 2V, Dead 2 AA Cells
5.2
7.2
6.8
9.5
s
Minimum CHRG/IADJ Pin Low Time
High
→Low→High
20
s
DONE Output Signal High
100k
Ω from VIN to DONE
3
V
DONE Output Signal Low
33A into DONE Pin
120
200
mV
DONE Leakage Current
VDONE = 3V, DONE NPN Off
1
100
nA
IGBTPWR Voltage Range
●
2.5
10
V
IGBT Input High Level
●
1.5
V
IGBT Input Low Level
●
0.5
V
IGBT Output Rise Time
IGBTPU Pin, COUT = 4000pF,
IGBTPWR = 5V, IGBTIN = 0V
→1.5V, 10%→90%
0.4
s
IGBT Output Fall Time
IGBTPD Pin, COUT = 4000pF,
IGBTPWR = 5V, IGBTIN = 1.5V
→0V, 90%→10%
0.13
s
Note 2: The LT3585 series is guaranteed to meet performance
specications from 0°C to 85°C. Specications over the – 40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls.
Note 3: Current limit is guaranteed by design and/or correlation to static
test.
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