参数资料
型号: LT3685IMSE#PBF
厂商: Linear Technology
文件页数: 16/24页
文件大小: 0K
描述: IC REG BUCK ADJ 2A 10MSOP
标准包装: 50
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.79 V ~ 20 V
输入电压: 3.6 V ~ 36 V
PWM 型: 电流模式
频率 - 开关: 200kHz ~ 2.4MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)裸露焊盘
包装: 管件
供应商设备封装: 10-MSOP
产品目录页面: 1332 (CN2011-ZH PDF)
LT3685
APPLICATIONS INFORMATION
Shorted and Reversed Input Protection
If the inductor is chosen so that it won’t saturate exces-
sively, an LT3685 buck regulator will tolerate a shorted
L1
V OUT
C2
output. There is another situation to consider in systems
where the output will be held high when the input to the
LT3685 is absent. This may occur in battery charging ap-
plications or in battery backup systems where a battery
or some other supply is diode OR-ed with the LT3685’s
output. If the V IN pin is allowed to ?oat and the RUN/SS
pin is held high (either by a logic signal or because it is
R RT
C C
R C
tied to V IN ), then the LT3685’s internal circuitry will pull
its quiescent current through its SW pin. This is ?ne if
your system can tolerate a few mA in this state. If you
R1
R2
ground the RUN/SS pin, the SW pin current will drop to
D1
C1
essentially zero. However, if the V IN pin is grounded while
the output is held high, then parasitic diodes inside the
GND
R PG
LT3685 can pull large currents from the output through
the SW pin and the V IN pin. Figure 7 shows a circuit that
will run only when the input voltage is present and that
VIAS TO LOCAL GROUND PLANE
VIAS TO V OUT VIAS TO SYNC
VIAS TO RUN/SS
VIAS TO PG
3685 F08
VIAS TO V IN
OUTLINE OF LOCAL
GROUND PLANE
protects against a shorted or reversed input.
D4
MBRS140
Figure 8. A Good PCB Layout Ensures Proper, Low EMI Operation
by these components should be as small as possible. These
V IN
V IN
BOOST
LT3685
components, along with the inductor and output capacitor,
should be placed on the same side of the circuit board,
RUN/SS
SW
V OUT
and their connections should be made on that layer. Place
V C
GND FB
BACKUP
a local, unbroken ground plane below these components.
The SW and BOOST nodes should be as small as possible.
Finally, keep the FB and V C nodes small so that the ground
traces will shield them from the SW and BOOST nodes.
3685 F07
Figure 7. Diode D4 Prevents a Shorted Input from
Discharging a Backup Battery Tied to the Output. It Also
Protects the Circuit from a Reversed Input. The LT3685
Runs Only When the Input is Present
The Exposed Pad on the bottom of the package must be
soldered to ground so that the pad acts as a heat sink. To
keep thermal resistance low, extend the ground plane as
much as possible, and add thermal vias under and near
the LT3685 to additional ground planes within the circuit
board and on the bottom side.
PCB Layout
For proper operation and minimum EMI, care must be
taken during printed circuit board layout. Figure 8 shows
the recommended component placement with trace,
ground plane and via locations. Note that large, switched
currents ?ow in the LT3685’s V IN and SW pins, the catch
diode (D1) and the input capacitor (C1). The loop formed
Hot Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LT3685 circuits. However, these capaci-
tors can cause problems if the LT3685 is plugged into a
live supply (see Linear Technology Application Note 88 for
3685fb
16
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