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| 型号： | LT3688EUF#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 22/28页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 0.8A DL 24QFN |
| 标准包装： | 91 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 0.8 V ~ 32.4 V |
| 输入电压： | 3.8 V ~ 36 V |
| PWM 型： | 电流模式，Burst Mode? |
| 频率 - 开关： | 500kHz ~ 2.1MHz |
| 电流 - 输出： | 800mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 24-QFN（4x4） |
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LT3688
APPLICATIONS INFORMATION
If WDO is low and RST goes low, then WDO will go
high. The WDE pin allows the user to turn on and off the
watchdog function. Leaving this pin open is okay and
will automatically enable the watchdog. It has an internal
weak pull-down to ground. The WDI pin has an internal
weak pull-up that keeps the WDI pin high. If watchdog is
disabled, leaving this pin open is acceptable.
V OUT1 (10V/DIV)
V OUT2 (10V/DIV)
RST1 (5V/DIV)
RST2 (5V/DIV)
WDO (5V/DIV)
WDI (10V/DIV)
Con?guration and Sequencing
Use the CONFIG pin to adjust the sequencing and the
behavior of the power-on reset and watchdog timers. The
table below shows all of the con?guration options.
Table 5. Con?guration Options
CONFIG
10ms/DIV
Figure 9a. CONFIG = HIGH
V OUT1 (10V/DIV)
V OUT2 (10V/DIV)
RST1 (5V/DIV)
3688 F09a
CONDITION
HIGH LOW OPEN
RST2 (5V/DIV)
Channel 1 starts before Channel 2
Channel 1 and Channel 2 start simultaneously
Watchdog operates only if Reset 1 Expires
×
×
×
×
WDO (5V/DIV)
WDI (10V/DIV)
Watchdog operates only if Reset 1 and Reset
2 Expire
×
×
10ms/DIV
3688 F09b
RST1 and RST2 high only if Timer 1 Expires
RST1 and RST2 use independent timers
×
×
×
Figure 9b. CONFIG = LOW
With the CONFIG pin tied high, V OUT1 will rise ?rst, as
shown in Figure 9a. After V OUT1 reaches V UV , V OUT2 will
start increasing. In addition, the reset timer for Channel 1
starts. Once V OUT2 reaches V UV , the reset timer for Channel 2
starts. Once the reset timers for both Channel 1 and Channel
2 have expired, the Watchdog will start operation.
V OUT1 (10V/DIV)
V OUT2 (10V/DIV)
RST1 (5V/DIV)
RST2 (5V/DIV)
WDO (5V/DIV)
WDI (10V/DIV)
With the CONFIG pin tied low, V OUT1 will rise ?rst. After
V OUT1 reaches V UV , V OUT2 will start increasing. The reset
timer will only start if both V OUT1 and V OUT2 are above V UV ,
as shown in Figure 9b. Once the reset timer programmed
by C POR1 expires, both RST1 and RST2 can pull high,
and the Watchdog will start operation. In this mode, tie
C POR2 to GND.
10ms/DIV
Figure 9c. CONFIG = OPEN
Figure 9. Startup Waveforms with the
Three Con?guration Settings
3688 F09c
With the CONFIG pin open, V OUT1 and V OUT2 can rise
simultaneously, as shown in ?gure 9c. After V OUT1 reaches
V UV the reset timer for Channel 1 starts. Once V OUT2
reaches V UV , the reset timer for Channel 2 starts. Once
the reset timer for Channel 1 has expired, the Watchdog
will start operation.
Selecting the Reset Timing Capacitors
The reset timeout period is adjustable in order to
accommodate a variety of microprocessor applications.
The reset timeout period, t RST , is adjusted by connecting
a capacitor, C POR , between the C POR pin and ground. The
value of this capacitor is determined by:
3688f
22
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