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参数资料
| 型号： | LT3689IUD-5#PBF |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | 1.95 A SWITCHING REGULATOR, 2160 kHz SWITCHING FREQ-MAX, PQCC16 |
| 封装： | 3 X 3 MM, LEAD FREE, PLASTIC, MO-220WEED-2, QFN-16 |
| 文件页数： | 16/32页 |
| 文件大小： | 2188K |
| 代理商： | LT3689IUD-5#PBF |
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LT3689/LT3689-5
23
3689fd
Example:switchingshouldnotstartuntiltheinputisabove
4.40V, and is to stop if the input falls below 4V.
V H = 4.40V,VL = 4V
R3 =
4.40V 4V
4A
4k = 95.3k
R4 =
1.26V
4.40V 1.26V
95.3k
– 4A
= 43.2k
(Nearest 1% Resistor)
Keep the connection from the resistor to the EN/UVLO
pin short and make sure the interplane or surface capaci-
tance to switching nodes is minimized. If high resistor
valuesareused,theEN/UVLOpinshouldbebypassedwith
a 1nF capacitor to prevent coupling problems from the
switch node.
Output Voltage Monitoring
The LT3689 provides power supply monitoring for micro-
processor-based systems. The features include power-on
reset (POR) and watchdog timing.
A precise internal voltage reference and glitch immune
precision POR comparator circuit monitor the LT3689
output voltage. The switcher’s output voltage must be
above90%ofprogrammedvalueforRSTnottobeasserted
(refer to the Timing Diagram). The LT3689 will assert RST
during power-up, power-down and brownout conditions.
Once the output voltage rises above the RST threshold,
the adjustable reset timer is started and RST is released
after the reset timeout period. On power-down, once the
output voltage drops below RST threshold, RST is held
at a logic low. The reset timer is adjustable using external
capacitors. The RST pin has a weak pull-up to the OUT pin.
The POR comparator is designed to be robust against FB
pinnoise,whichcouldpotentiallyfalsetriggertheRSTpin.
The POR comparator lowpass filters the first stage of the
comparator.Thisfilterintegratestheoutputofthecompara-
torbeforeassertingtheRST.Thebenefitofaddingthisfilter
is that any transients at the buck regulator’s output must
be of sufficient magnitude and duration before it triggers
a logic change in the output (see the Typical Transient vs
POR Comparator Overdrive in the Typical Performance
Characteristics section). This prevents spurious resets
caused by output voltage transients such as load steps
or short brownout conditions without sacrificing the DC
reset threshold accuracy.
Watchdog
The LT3689 includes an adjustable watchdog timer that
monitors a P’s activity. If a code execution error occurs
in a P, the watchdog will detect this error and will set the
WDO low. This signal can be used to interrupt a routine
or to reset a microprocessor.
The watchdog is operated either in timeout or window
mode. In timeout mode, the microprocessor needs to
toggle the WDI pin before the watchdog timer expires, to
keep the WDO pin high. If no WDI pulse (either positive or
negative)appearsduringtheprogrammedtimeoutperiod,
then the circuitry will pull WDO low. During normal opera-
tion, the WDI input signal’s high to low, and low to high
transition periods should be set lower than the watchdog’s
programmed time to keep WDO inactive.
In window mode, the watchdog circuitry is triggered by
negativeedgesontheWDIpin.Thewindowmoderestricts
the WDI pin’s negative going pulses to appear inside a
programmed time window (see the Timing Diagram) to
prevent WDO from going low. If more than two pulses are
registeredinthewatchdoglowerboundaryperiod,the WDO
is forced to go low. The WDI edges are ignored while the
CWDT capacitor charges from 0V to 200mV right after a
low to high transition on the WDO or RST pin. The WDO
also goes low if no negative edge is supplied to the WDI
pin in the watchdog upper boundary period. During a code
executionerror,themicroprocessorwilloutputWDIpulses
that would be either too fast or too slow. This condition
will assert WDO and force the microprocessor to reset the
program. In window mode, the WDI signal frequency is
bounded by an upper and lower limit for normal operation.
The WDI input frequency period should be higher than the
tWDL period, and lower than the tWDU period, to keep WDO
high under normal conditions. The window mode’s tWDL
and tWDU times have a fixed ratio of 31 between them.
These times can be increased or decreased by adjusting
an external capacitor on the CWDT pin.
APPLICATIONS INFORMATION
相关PDF资料 |
PDF描述 |
|---|---|
| LT3689EMSE-5#TRPBF | 1.95 A SWITCHING REGULATOR, 2160 kHz SWITCHING FREQ-MAX, PDSO16 |
| LT3689EUD-5#TRPBF | 1.95 A SWITCHING REGULATOR, 2160 kHz SWITCHING FREQ-MAX, PQCC16 |
| LT3689EMSE-5#PBF | 1.95 A SWITCHING REGULATOR, 2160 kHz SWITCHING FREQ-MAX, PDSO16 |
| LT3689IUD-5#TRPBF | 1.95 A SWITCHING REGULATOR, 2160 kHz SWITCHING FREQ-MAX, PQCC16 |
| LT3689IMSE-5#TRPBF | 1.95 A SWITCHING REGULATOR, 2160 kHz SWITCHING FREQ-MAX, PDSO16 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LT3689IUD-5-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:700mA Step-Down Regulator with Power-On Reset and Watchdog Timer |
| LT3689IUD-PBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:700mA Step-Down Regulator with Power-On Reset and Watchdog Timer |
| LT3689IUD-TRPBF | 制造商:LINER 制造商全称:Linear Technology 功能描述:700mA Step-Down Regulator with Power-On Reset and Watchdog Timer |
| LT3690 | 制造商:LINER 制造商全称:Linear Technology 功能描述:36V, 4A, 1.5MHz Synchronous Step-Down Switching Regulator |
| LT3690EUFE#PBF | 功能描述:IC REG BUCK SYNC ADJ 4A 26QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON（1.45x1） 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2 |
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