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参数资料
| 型号： | LT3724MPFE#TR |
| 厂商： | LINEAR TECHNOLOGY CORP |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING CONTROLLER, 225 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封装： | 4.40 MM, PLASTIC, TSSOP-16 |
| 文件页数： | 8/26页 |
| 文件大小： | 309K |
| 代理商： | LT3724MPFE#TR |
LT3724
16
3724fd
APPLICATIONS INFORMATION
The desired soft-start rise time (tSS) is programmed via
a programming capacitor CSS1, using a value that cor-
responds to 2A average current during the soft-start
interval. This capacitor value follows the relation:
CSS1=
2 10–6 tSS
VOUT
RSS is typically set to 200k for most applications.
Considerations for Low-Voltage Output Applications
The LT3724 CSS pin biases to 220mV during the soft-start
cycle, and this voltage is increased at Figure 4 node “A” by
the 2A signal current through RSS, so the output has to
reach this value before the soft-start function is engaged.
The value of this output soft-start startup voltage offset
(VOUT(SS)) follows the relation:
VOUT(SS) = 220mV + RSS 2 10–6
Which is typically 0.64V for RSS = 200k.
In some low voltage output applications, it may be desir-
able to reduce the value of this soft-start startup voltage
offset. This is possible by reducing the value of RSS. With
reduced values of RSS, the signal component caused by
voltage ripple on the output must be minimized for proper
soft-start operation.
Peak-to-peakoutputvoltageripple(VOUT)willbeimposed
on node “A” through the capacitor CSS1. The value of RSS
can be set using the following equation:
RSS =
VOUT
1.3 10–6
ItisimportanttouselowESRoutputcapacitorsforLT3724
voltage converter designs to minimize this ripple voltage
component. A design with an excessive ripple component
can be evidenced by observing the VC pin during the start
cycle.
The soft-start cycle should be evaluated to verify that the
reduced RSS value allows operation without excessive
modulation of the VC pin before finalizing the design.
If VC pin has an excessive ripple component during the
soft-startcycle,converteroutputrippleshouldbereduced.
Thisistypicallyaccomplishedbyincreasingoutputcapaci-
tance and/or reducing output capacitor ESR.
External Current Limit Foldback Circuit
An additional startup voltage offset can occur during the
period before the LT3724 soft-start circuit becomes ac-
tive. Before the soft-start circuit throttles back the VC pin
in response to the rising output voltage, current as high
as the peak programmed current limit (IMAX) can flow in
the switched inductor. Switching will stop once the soft-
start circuit takes hold and reduces the voltage on the
VC pin, but the output voltage will continue to increase
as the stored energy in the inductor is transferred to the
output capacitor. With IMAX in the inductor, the resulting
leading-edge rise on VOUT due to energy stored in the
inductor follows the relation:
VOUT =IMAX
L
COUT
1/2
Figure 6. Desirable Soft-Start Characteristic
Figure 5. Soft-Start Characteristic
Showing Excessive Ripple Component
TIME, 250s/DIV
V(VC)
VOUT(SS)
VOUT
3724 F05
TIME, 250s/DIV
3724F06
V(VC)
VOUT(SS)
VOUT
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