参数资料
型号: LT3757EDD#PBF
厂商: Linear Technology
文件页数: 19/36页
文件大小: 0K
描述: IC REG CTRLR BST FLYBK INV 10DFN
产品培训模块: LT3757 and LT3758 - Boost, Flyback, SEPIC and Inverting Controllers
特色产品: LT3757 - Inverting Controller
标准包装: 121
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
电源电压: 2.9 V ~ 40 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 10-WFDFN 裸露焊盘
包装: 管件
产品目录页面: 1332 (CN2011-ZH PDF)
LT3757/LT3757A
APPLICATIONS INFORMATION
I LP(MAX) = I SW(MAX) =
D 2MAX ? V 2IN(MIN) ? h
L P =
D2 2 ? (V OUT + V D )
L S =
I LS(MAX) = I D(MAX) =
I LP(RMS) = 2 ? I LP(MAX) ?
I LS(RMS) = 2 ? I LS(MAX) ?
N P L P
N S
L S
V 2SN ? V SN ? V OUT ?
R SN = 2 ?
FlybackConverter:TransformerDesignfor
Discontinuous Mode Operation
The transformer design for discontinuous mode of opera-
tion is chosen as presented here. According to Figure 8,
the minimum D3 (D3 MIN ) occurs when the converter
has the minimum V IN and the maximum output power
(P OUT ). Choose D3 MIN to be equal to or higher than 10%
to guarantee the converter is always in discontinuous
mode operation (choosing higher D3 allows the use of low
inductances, but results in a higher switch peak current).
The user can choose a D MAX as the start point. Then, the
maximum average primary currents can be calculated by
the following equation:
P OUT(MAX)
D MAX ? V IN(MIN) ? h
where h is the converter efficiency.
If the flyback converter has multiple outputs, P OUT(MAX)
is the sum of all the output power.
The maximum average secondary current is:
I OUT(MAX)
D2
where:
D2 = 1 – D MAX – D3
the primary and secondary RMS currents are:
D MAX
3
D2
3
According to Figure 8, the primary and secondary peak
currents are:
I LP(PEAK) = I SW(PEAK) = 2 ? I LP(MAX)
I LS(PEAK) = I D(PEAK) = 2 ? I LS(MAX)
The primary and second inductor values of the flyback
converter transformer can be determined using the fol-
lowing equations:
2 ? P OUT(MAX) ? f
2 ? I OUT(MAX) ? f
The primary to second turns ratio is:
=
Flyback Converter: Snubber Design
Transformer leakage inductance (on either the primary or
secondary) causes a voltage spike to occur after the MOS-
FET turn-off. This is increasingly prominent at higher load
currents, where more stored energy must be dissipated.
In some cases a snubber circuit will be required to avoid
overvoltage breakdown at the MOSFET’s drain node. There
are different snubber circuits, and Application Note 19 is
a good reference on snubber design. An RCD snubber is
shown in Figure 7.
The snubber resistor value (R SN ) can be calculated by the
following equation:
N P
N S
I 2SW(PEAK) ? L LK ? f
3757afd
19
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