参数资料
型号: LT3971IDD#PBF
厂商: Linear Technology
文件页数: 11/28页
文件大小: 0K
描述: IC REG BUCK ADJ 1.2A 10DFN
标准包装: 121
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1.19 V ~ 30 V
输入电压: 4.3 V ~ 38 V
PWM 型: 电流模式,Burst Mode?
频率 - 开关: 200kHz ~ 2MHz
电流 - 输出: 1.2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 10-WFDFN 裸露焊盘
包装: 管件
供应商设备封装: 10-DFN(3x3)
LT3971/LT3971-3.3/LT3971-5
APPLICATIONS INFORMATION
R1 = R2 ? OUT ? 1 ?
5μs/DIV
feedbackresistorsandalowleakageSchottkycatchdiode
in applications utilizing the ultralow quiescent current
performance of the LT3971. The feedback resistors should
preferably be on the order of MΩ and the Schottky catch
diode should have less than 1μA of typical reverse leak-
age at room temperature. These two considerations are
reiterated in the FB Resistor Network and Catch Diode
Selection sections.
It is important to note that another way to decrease the
pulse frequency is to increase the magnitude of each
single current pulse. However, this increases the output
voltage ripple because each cycle delivers more power to
the output capacitor. The magnitude of the current pulses
was selected to ensure less than 15mV of output ripple in
a typical application. See Figure 2.
V SW
5V/DIV
I L
500mA/DIV
V OUT
20mV/DIV
3971 F02
V IN = 12V
V OUT = 3.3V
I LOAD = 10mA
Figure 2. Burst Mode Operation
While in Burst Mode operation, the burst frequency and
the charge delivered with each pulse will not change with
output capacitance. Therefore, the output voltage ripple
will be inversely proportional to the output capacitance.
In a typical application with a 22μF output capacitor, the
output ripple is about 10mV, and with a 47μF output ca-
pacitor the output ripple is about 5mV. The output voltage
ripple can continue to be decreased by increasing the
output capacitance.
At higher output loads (above 92mA for the front page
application) the LT3971 will be running at the frequency
programmed by the R T resistor, and will be operating in
standard PWM mode. The transition between PWM and low
ripple Burst Mode operation will exhibit slight frequency
jitter, but will not disturb the output voltage.
To ensure proper Burst Mode operation, the SYNC pin
must be grounded. When synchronized with an external
clock, the LT3971 will pulse skip at light loads. The qui-
escent current will significantly increase to 1.5mA in light
load situations when synchronized with an external clock.
Holding the SYNC pin high yields no advantages in terms
of output ripple or minimum load to full frequency, so is
not recommended.
FB Resistor Network
The output voltage is programmed with a resistor divider
between the output and the FB pin. Choose the resistor
values according to:
? V ?
? 1.19V ?
Reference designators refer to the Block Diagram. 1%
resistors are recommended to maintain output voltage
accuracy.
The total resistance of the FB resistor divider should be
selected to be as large as possible to enhance low current
performance. The resistor divider generates a small load
on the output, which should be minimized to optimize the
low supply current at light loads.
When using large FB resistors, a 10pF phase lead capacitor
should be connected from V OUT to FB.
The LT3971-3.3 and LT3971-5 contain an internal 10M FB
resistor divider as well as an internal phase lead capacitor.
Setting the Switching Frequency
The LT3971 uses a constant frequency PWM architecture
that can be programmed to switch from 200kHz to 2MHz
by using a resistor tied from the RT pin to ground. A table
showing the necessary R T value for a desired switching
frequency is in Table 1.
3971fd
11
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