参数资料
型号: LT4254CGN#TR
厂商: Linear Technology
文件页数: 10/16页
文件大小: 232K
描述: IC CTLR HOTSWAP POS 16-SSOP
标准包装: 2,500
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: 10.8 V ~ 36 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-SSOP
包装: 带卷 (TR)
LT4254
10
4254fb
APPLICATIO  S I FOR  ATIO
U
U
U
Resistor R7 compensates the current control loop while
R6 prevents high frequency oscillations in Q1.
When the power pins first make contact, transistor Q1 is
held off. If the voltage on the V
CC
 pin is between the
externally programmed undervoltage and overvoltage
thresholds, and the voltage on the TIMER pin is less than
4.65V (typ), transistor Q1 will be turned on (Figure 6). The
voltage at the GATE pin rises with a slope equal to 35礎/
C1 and the supply inrush current is set at:
I
INRUSH
 = C
L
 " 35礎/C1
If the voltage across the current sense resistor R5 reaches
V
SENSETRIP
, the inrush current will be limited by the
internal current limit circuitry. The voltage on the GATE pin
is adjusted to maintain a constant voltage across the sense
resistor and the TIMER pin begins to charge.
When the FB pin voltage goes above the low-to-high V
FB
threshold, the PWRGD pin goes high.
Short-Circuit Protection
The LT4254 features a programmable foldback current
limit with an electronic circuit breaker that protects against
short circuits or excessive load currents. The current limit
is set by placing a sense resistor (R5) between V
CC
 and
SENSE.
To limit excessive power dissipation in the pass transistor
and to reduce voltage spikes on the input supply during
short-circuit conditions at the output, the current folds
Figure 5. 2A, 24V Application
4254 F05
R5
0.025&
LT4254
SENSE
13
10
5
7
8
16
15
1
2
4
9
V
CC
GATE
FB
PWRGD
RETRY
UV
OV
TIMER
GND
V
IN
24V
GND
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R3
40.2k
R2
40.2k
R1
324k
R7
100&
R9
40.2k
R6
10&
R8
140k
PWRGD
V
OUT
24V
1.5A
R4
27k
C
L
C2
33nF
C3
0.1礔
C1
10nF
OPEN
UV = 20V
OV = 40V
PWRGD = 18V
back as a function of the output voltage, which is sensed
internally on the FB pin.
When the voltage at the FB pin is 0V, the current limit
circuit drives the GATE pin to force a constant 12mV drop
across the sense resistor. As the output at the FB pin
increases, the voltage across the sense resistor increases
until the FB pin reaches 2V, at which point the voltage
across the sense resistor is held constant at 50mV (see
Figure 7). The current limit threshold is calculated as:
I
LIMIT
 = 50mV/R5
where R5 is the sense resistor.
For a 0.025& sense resistor, the current limit is set at
2000mA and folds back to 600mA when the output is
shorted to ground. Thus, MOSFET dissipation under short-
circuit conditions is reduced from 36W to12W. See the
Figure 6. Start-Up Waveforms
2.5ms/DIV
4254 F06
I
OUT
500mA/DIV
PWRGD
20V/DIV
V
OUT
20V/DIV
GATE
20V/DIV
C
L
 = 185礔
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LT4256 制造商:LINER 制造商全称:Linear Technology 功能描述:High Voltage Surge