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参数资料
| 型号： | LT6105IMS8#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 3/20页 |
| 文件大小： | 0K |
| 描述： | IC AMP R-R CURRENT SENSE 8-MSOP |
| 标准包装： | 2,500 |
| 放大器类型： | 电流检测 |
| 电路数： | 1 |
| 转换速率： | 2 V/µs |
| -3db带宽： | 100kHz |
| 电压 - 输入偏移： | 100µV |
| 电流 - 电源： | 250µA |
| 电流 - 输出 / 通道： | 1mA |
| 电压 - 电源，单路/双路(±)： | 2.85 V ~ 36 V，±1.425 V ~ 18 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 带卷 (TR) |
LT6105
11
6105fa
PIN FUNCTIONS
–IN (Pin 1/Pin 1): Negative Sense Input Terminal.
Negative sense voltage input will remain functional for
voltages up to 44V, referred to V–. Connect –IN to an
external gain-setting resistor RIN1 (RIN1 = RIN2) to set
the gain.
V+ (Pin 2/Pin 2):
Power Supply Voltage. This pin supplies
current to the amplier and can operate from 2.85V to 36V,
independent of the voltages on the –IN or +IN pins.
V– (Pin 3/Pin 4):
Negative Power Supply Voltage or Ground
for Single Supply Operation.
VOUT (Pin 4/Pin 5): Voltage Output:
VOUT = AV (VSENSE ± VOS)
VOS is the input offset voltage. AV is the gain set by exter-
nal RIN1, RIN2, ROUT. AV = ROUT/RIN1, for RIN1 = RIN2.
NC (Pin 5/Pins 3, 6, 7): Not Connected Internally.
+IN (Pin 6/Pin 8): Positive Sense Input Terminal.
Connecting a source to VS+ and a load to VS– will allow the
LT6105 to monitor the current through RSENSE, refer to
Figure 1. Connect +IN to an external gain-setting resistor
RIN2 to set the gain. +IN remains functional for voltages
up to 44V, referred to V–.
Exposed Pad (Pin 7) DFN Only: V–. The Exposed Pad is
connected to the V– pin. It should be connected to the
V– trace of the PCB, or left oating.
(DCB/MS8)
BLOCK DIAGRAM
ROUT
VSENSE
RSENSE
RIN2
RIN1
VS+
VS–
LT6105
TO LOAD
SOURCE
0V TO 44V
VOUT = VSENSE
ROUT
RIN2
VOUT = VSENSE
WHERE RIN = RIN1 = RIN2
ROUT
RIN
AV =
ROUT
RIN
VOUT
V+
–IN
+IN
V –
SET RIN1 = RIN2 FOR BEST ACCURACY
IF RIN1 ≠ RIN2, THEN
RIN1, RIN2, ROUT ARE EXTERNAL RESISTORS
V(–IN) > 1.6V:
VOUT = VSENSE
ROUT
RIN1
V(–IN) < 1.6V:
6105 F01
–
+
–
+
A1
Q2
Q3
Q1
A2
Figure 1. Simplied Block Diagram
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