参数资料
| 型号： | LT6553CGN#TR |
| 厂商： | Linear Technology |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC AMP VIDEO TRIPLE GAIN2 16SSOP |
| 标准包装： | 2,500 |
| 应用： | 通用 |
| 电路数： | 3 |
| -3db带宽： | 650MHz |
| 转换速率： | 2500 V/µs |
| 电流 - 电源： | 8mA |
| 电流 - 输出 / 通道： | 70mA |
| 电压 - 电源，单路/双路(±)： | 4.5 V ~ 12 V，±2.25 V ~ 6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 带卷 (TR) |
LT6553
8
6553f
Power Supplies
The LT6553 is optimized for
±5V supplies but can be
operated on as little as
±2.25V or a single 4.5V supply and
as much as
±6V or a single 12V supply. Internally, each
supply is independent to improve channel isolation. Do
not leave any supply pins disconnected or the part may
not function correctly!
Enable/Shutdown
The LT6553 has a TTL compatible shutdown mode con-
trolled by the EN pin and referenced to the DGND pin. If the
amplifier will be enabled at all times, the EN pin can be
connected directly to DGND. If the enable function is
desired, either driving the pin above 2V or allowing the
internal 46k pull-up resistor to pull the EN pin to the top rail
will disable the amplifier. When disabled, the DC output
impedance will rise to approximately 700
through the
internal feedback and gain resistors. Supply current into
the amplifier in the disabled state will be primarily through
V+ and approximately equal to (V+ – VEN)/46k.
It is important that the two following constraints on the
DGND pin and the EN pin are always followed:
V+ – VDGND ≥ 3V
VEN – VDGND ≤ 5.5V
Split supplies of
±3V to ±5.5V will satisfy these require-
ments with DGND connected to 0V.
In single supply applications above 5.5V, an additional
resistor may be needed from the EN pin to DGND if the pin
is ever allowed to float. For example, on a 12V single
supply, a 33k resistor would protect the pin from floating
too high while still allowing the internal pull-up resistor to
disable the part.
On dual
±2.25V supplies, connecting the EN and DGND
pins to V– is the easiest way of ensuring that V+ – VDGND
is more than 3V.
The DGND pin should not be pulled above the EN pin since
doing so will turn on an ESD protection diode. If the EN pin
voltage is forced a diode drop below the DGND pin, current
should be limited to 10mA or less.
The enable/disable times of the LT6553 are fast when
driven with a logic input. Turn on (from 50% EN input to
50% output) typically occurs in less than 50ns. Turn off is
slower, but is nonetheless below 300ns.
Input Considerations
The LT6553 input voltage range is from V– + 1V to V+ – 1V.
Therefore, on split supplies the LT6553 input range is
always larger than the output swing. On a single positive
supply, however, the input range limits the output low
swing to 2V (1V multiplied by the internal gain of 2).
The inputs can be driven beyond the point at which the
output clips so long as input currents are limited to below
±10mA. Continuing to drive the input beyond the output
limit can result in increased current drive and slightly
increased swing, but will also increase supply current and
may result in delays in transient response at larger levels
of overdrive.
Layout and Grounding
It is imperative that care is taken in PCB layout in order to
utilize the very high speed and very low crosstalk of the
LT6553. Separate power and ground planes are highly
recommended and trace lengths should be kept as short
as possible. If input or output traces must be run over a
distance of several centimeters, they should use a con-
trolled impedance with matching series and shunt resis-
tances (nominally 75
) to maintain signal fidelity.
Series termination resistors should be placed as close to
the output pins as possible to minimize output capaci-
tance. See the Typical Performance Characteristics sec-
tion for a plot of frequency response with various output
capacitors—only 10pF of parasitic output capacitance
causes 6dB of peaking in the frequency response!
Low ESL/ESR bypass capacitors should be placed as close
to the positive and negative supply pins as possible. One
4700pF ceramic capacitor is recommended for both V+
and V–. Additional 470pF ceramic capacitors with minimal
trace length on each supply pin will further improve AC and
transient response as well as channel isolation. For high
current drive and large-signal transient applications, addi-
tional 1
F to 10F tantalums should be added on each
supply. The smallest value capacitors should be placed
closest to the package.
APPLICATIO S I FOR ATIO
WU
U
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相关代理商/技术参数 |
参数描述 |
|---|---|
| LT6553IGN | 功能描述:IC AMP VIDEO TRIPLE GAIN2 16SSOP RoHS:否 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 标准包装:1,000 系列:- 应用:驱动器 输出类型:差分 电路数:3 -3db带宽:350MHz 转换速率:1000 V/µs 电流 - 电源:14.5mA 电流 - 输出 / 通道:60mA 电压 - 电源，单路/双路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安装类型:表面贴装 封装/外壳:20-VFQFN 裸露焊盘 供应商设备封装:20-QFN 裸露焊盘（4x4） 包装:带卷 (TR) |
| LT6553IGN#PBF | 功能描述:IC AMP VIDEO TRIPLE GAIN2 16SSOP RoHS:是 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 标准包装:1,000 系列:- 应用:驱动器 输出类型:差分 电路数:3 -3db带宽:350MHz 转换速率:1000 V/µs 电流 - 电源:14.5mA 电流 - 输出 / 通道:60mA 电压 - 电源，单路/双路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安装类型:表面贴装 封装/外壳:20-VFQFN 裸露焊盘 供应商设备封装:20-QFN 裸露焊盘（4x4） 包装:带卷 (TR) |
| LT6553IGN#TR | 功能描述:IC AMP VIDEO TRIPLE GAIN2 16SSOP RoHS:否 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 标准包装:1,000 系列:- 应用:驱动器 输出类型:差分 电路数:3 -3db带宽:350MHz 转换速率:1000 V/µs 电流 - 电源:14.5mA 电流 - 输出 / 通道:60mA 电压 - 电源，单路/双路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安装类型:表面贴装 封装/外壳:20-VFQFN 裸露焊盘 供应商设备封装:20-QFN 裸露焊盘（4x4） 包装:带卷 (TR) |
| LT6553IGN#TRPBF | 功能描述:IC AMP VIDEO TRIPLE GAIN2 16SSOP RoHS:是 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 标准包装:1,000 系列:- 应用:驱动器 输出类型:差分 电路数:3 -3db带宽:350MHz 转换速率:1000 V/µs 电流 - 电源:14.5mA 电流 - 输出 / 通道:60mA 电压 - 电源，单路/双路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安装类型:表面贴装 封装/外壳:20-VFQFN 裸露焊盘 供应商设备封装:20-QFN 裸露焊盘（4x4） 包装:带卷 (TR) |
| LT6554 | 制造商:LINER 制造商全称:Linear Technology 功能描述:650MHz Gain of 1 Triple Video Buffer |
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