参数资料
| 型号： | LT6554CGN#TR |
| 厂商： | Linear Technology |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC BUFFER VID TRPL 650MHZ 16SSOP |
| 标准包装： | 2,500 |
| 应用： | 缓冲器 |
| 电路数： | 3 |
| -3db带宽： | 650MHz |
| 转换速率： | 2500 V/µs |
| 电流 - 电源： | 8mA |
| 电流 - 输出 / 通道： | 70mA |
| 电压 - 电源，单路/双路(±)： | 4.5 V ~ 12 V，±2.25 V ~ 6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 带卷 (TR) |
LT6554
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6554fa
Power Supplies
The LT6554 is optimized for ±5V supplies but can be
operated on as little as ±2.25V or a single 4.5V supply and
as much as ±6V or a single 12V supply. Internally, each
supply is independent to improve channel isolation. Do
not leave any supply pins disconnected!
Enable/Shutdown
The LT6554 has a TTL compatible shutdown mode con-
trolled by the EN pin and referenced to the DGND pin. If the
amplifier will be enabled at all times, the EN pin can be
connected directly to DGND. If the enable function is
desired, either driving the pin above 2V or allowing the
internal 46k pull-up resistor to pull the EN pin to the top rail
will disable the amplifier. When disabled, the output will
become very high impedance. Supply current into the
amplifier in the disabled state will be primarily through V+
and approximately equal to (V+ – VEN)/46k.
It is important that the two following constraints on the
DGND pin and the EN pin are always followed:
V+ – VDGND ≥ 3V
VEN – VDGND ≤ 5.5V
Split supplies of ±3V to ±5.5V will satisfy these require-
ments with DGND connected to 0V.
In single supply applications above 5.5V, an additional
resistor may be needed from the EN pin to DGND if the pin
is ever allowed to float. For example, on a 12V single
supply, a 33k resistor to ground would protect the pin from
floating too high while still allowing the internal pull-up
resistor to disable the part.
On dual ±2.25V supplies, connecting the EN and DGND
pins to V– is the easiest way of ensuring that V+ – VDGND
is more than 3V.
The DGND pin should not be pulled above the EN pin since
doing so will turn on an ESD protection diode. If the EN pin
voltage is forced a diode drop below the DGND pin, current
should be limited to 10mA or less.
The enable/disable times of the LT6554 are fast when
driven with a logic input. Turn on (from 50% EN input to
50% output) typically occurs in less than 50ns. Turn off is
slower, but is nonetheless below 300ns.
Input Considerations
The LT6554 input voltage range is from V– + 1V to V+ – 1V
and is therefore larger than the output swing. The inputs
can be driven beyond the point at which the output clips so
long as input currents are limited to below ±10mA.
Layout and Grounding
It is imperative that care is taken in PCB layout in order to
utilize the very high speed and very low crosstalk of the
LT6554. Separate power and ground planes are highly
recommended and trace lengths should be kept as short
as possible. If input traces must be run over a distance of
several centimeters, they should use a controlled imped-
ance with either series or shunt terminations (nominally
50 or 75) to maintain signal fidelity.
Care should be taken to minimize capacitance on the
LT6554’s output traces by increasing spacing between
traces and adjacent metal and by eliminating metal planes
in underlying layers. To drive cable or traces longer than
several centimeters, using the LT6553 with its fixed gain
of +2 in conjunction with series and load termination
resistors may provide better results.
A plot of LT6554 performance driving a 1k load with
various trace lengths is shown in Figure 1. All data is from
a 4-layer board with 2oz copper, 18mil of board layer
thickness to the ground plane, a trace width of 12mils and
spacing to adjacent metal of 18mils. The 0.2cm output
trace places the 1k resistor as close to the part as possible,
while the other curves show the load resistor consecu-
tively further away. The worst case, 4cm, trace has almost
10pF of parasitic capacitance.
In order to counteract any peaking in the frequency re-
sponse from driving a capacitive load, a series resistance
can be inserted in the line at the output of the part to flatten
the response. Figure 2 shows the frequency response with
the same 4cm trace from Figure 1, now with a 10 series
resistor inserted near the output pin of the LT6554. Note
that using a 10 series resistor with a 1k load only
decreases the output amplitude by 0.1dB or 1% and has a
minimal effect on the bandwidth of the system. See the
graph labeled “Maximum Capacitive Load vs Output Se-
ries Resistor” in the Typical Performance Characteristics
section for more information.
APPLICATIO S I FOR ATIO
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| LT6554IGN | 功能描述:IC BUFFER VID TRPL 650MHZ 16SSOP RoHS:否 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 标准包装:1,000 系列:- 应用:驱动器 输出类型:差分 电路数:3 -3db带宽:350MHz 转换速率:1000 V/µs 电流 - 电源:14.5mA 电流 - 输出 / 通道:60mA 电压 - 电源，单路/双路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安装类型:表面贴装 封装/外壳:20-VFQFN 裸露焊盘 供应商设备封装:20-QFN 裸露焊盘（4x4） 包装:带卷 (TR) |
| LT6554IGN#PBF | 功能描述:IC BUFFER VID TRPL 650MHZ 16SSOP RoHS:是 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 标准包装:1,000 系列:- 应用:驱动器 输出类型:差分 电路数:3 -3db带宽:350MHz 转换速率:1000 V/µs 电流 - 电源:14.5mA 电流 - 输出 / 通道:60mA 电压 - 电源，单路/双路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安装类型:表面贴装 封装/外壳:20-VFQFN 裸露焊盘 供应商设备封装:20-QFN 裸露焊盘（4x4） 包装:带卷 (TR) |
| LT6554IGN#TR | 功能描述:IC BUFFER VID TRPL 650MHZ 16SSOP RoHS:否 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 标准包装:1,000 系列:- 应用:驱动器 输出类型:差分 电路数:3 -3db带宽:350MHz 转换速率:1000 V/µs 电流 - 电源:14.5mA 电流 - 输出 / 通道:60mA 电压 - 电源，单路/双路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安装类型:表面贴装 封装/外壳:20-VFQFN 裸露焊盘 供应商设备封装:20-QFN 裸露焊盘（4x4） 包装:带卷 (TR) |
| LT6554IGN#TRPBF | 功能描述:IC BUFFER VID TRPL 650MHZ 16SSOP RoHS:是 类别:集成电路 (IC) >> 线性 - 放大器 - 视频放大器和频缓冲器 系列:- 标准包装:1,000 系列:- 应用:驱动器 输出类型:差分 电路数:3 -3db带宽:350MHz 转换速率:1000 V/µs 电流 - 电源:14.5mA 电流 - 输出 / 通道:60mA 电压 - 电源，单路/双路(±):5 V ~ 12 V，±2.5 V ~ 6 V 安装类型:表面贴装 封装/外壳:20-VFQFN 裸露焊盘 供应商设备封装:20-QFN 裸露焊盘（4x4） 包装:带卷 (TR) |
| LT6555 | 制造商:LINER 制造商全称:Linear Technology 功能描述:650MHz Gain of 2 Triple 2:1Video Multiplexer |
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