参数资料
型号: LT6700CS6-3#TRMPBF
厂商: Linear Technology
文件页数: 8/20页
文件大小: 0K
描述: IC COMP DUAL 400MV REF TSOT23-6
标准包装: 1
系列: Over-The-Top®
类型: 通用
元件数: 2
输出类型: 开路集电极
电压 - 电源,单路/双路(±): 1.4 V ~ 18 V
电流 - 输入偏压(最小值): 0.01µA @ 18V
电流 - 静态(最大值): 16µA
传输延迟(最大): 29µs
磁滞: 11mV
工作温度: 0°C ~ 70°C
封装/外壳: SOT-23-6 细型,TSOT-23-6
安装类型: 表面贴装
包装: 标准包装
产品目录页面: 1324 (CN2011-ZH PDF)
其它名称: LT6700CS6-3#TRMPBFDKR
LT6700/LT6700HV
16
6700123fh
For more information www.linear.com/LT6700
APPLICATIONS INFORMATION
Figure 3. Isolated PWM or ∑ Converter
LT6700-1
VS
10k
GND
+INA
–INB OUTB
OUTA
100k*
0.22F
+
412k*
10k**
470
Lithium
COIN CELL
10k
750
10k
750**
3V/5V
ΔΣ
SAMPLE
IN
MOC-207
MOC-207**
PWM OUT
(OR ΔΣ SENSE)
2
1
5
6
5
6
2
1
0.1F
3V NOM (IS < 3mA)
5 VREF = 2V
6700123 F03
22F
1% METAL FILM
DELETE FOR PWM MODE
CONNECT FOR PWM MODE
OPTIMIZED FOR 2kHz ΔΣ SAMPLING, fPWM(MAX) ≈ 0.6kHz
*
**
309k*
NC7S14
309k*
VIN
0V TO 2V
+
Figure 2. Micropower Thermostat/Temperature Alarm
LT6700-1
VS
10k
GND
+INA
–INB OUTB
OUTA
499k
RTH
T
RTH = 1M (e.g., YSI 44015, 1.00M AT 25°C)
RSET = RTH AT TSET
*RESISTANCE MAY REQUIRE OPTIMIZATION FOR OPERATION
OVER INTENDED RTH AND VSUPPLY RANGES
HYSTERESIS ZONE ≈0.4°C
RSET
2 VREF
499k
220k
220k*
3.3F
1.4V TO 18V
(IS ≈ 10A)
0.1F
T < TSET
6700123 F02
charges and discharges in a shallow, controlled fashion.
The multiplied reference signal also contains ripple that is
the hysteresis multiplied by the same factor, so additional
filtering is performed at the sense node of the bridge to
prevent comparator chatter in the section A comparator,
which is performing the actual conditional decision for
the circuit.
Instrumentation Grade Pulse Width Modulator (PWM)
Comparators with hysteresis are frequently employed
to make simple oscillator structures, and the LT6700/
LT6700HVlendsitselfnicelytoformingacharge-balancing
PWM function. The circuit shown in Figure 3 forms a PWM
that is intended to transmit an isolated representation of a
voltage difference, rather like an isolated instrumentation
amplifier. The section B comparator is used to generate a
2VreferencesupplylevelfortheCMOSNOTgate(inverter),
whichservesastheprecisionswitchelementforthecharge
balancer. The heart of the charge balancer is the section A
comparator, which is detecting slight charge or discharge
states on the 0.22F “integration” capacitor as it remains
balanced at ≈400mV by feedback through the NOT gate.
The input sense voltage, VIN, is converted to an imbal-
ance current that the NOT gate duty cycle is continually
correcting for, thus the digital waveform at the section A
comparator output is a PWM representation of VIN with
respect to the 2V “full scale.” In this particular circuit, the
PWMinformationdrivestheLEDofanopto-coupler,allow-
ing the VIN information to be coupled across a dielectric
barrier. As an additional option to the circuit, the feedback
loopcanbebrokenandasecondopto-coupleremployedto
provide the charge balance management. This configura-
tion allows for clocking the comparator output (externally
to this circuit) and providing synchronous feedback such
that a simple Δ∑ voltage-to-frequency conversion can be
formedifdesired.Approximately11-bitaccuracyandnoise
performance was observed in a one second integration
period for duty factors from 1% to 99%.
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