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参数资料
| 型号： | LTC1046IS8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/12页 |
| 文件大小： | 0K |
| 描述： | IC REG SWITCHD CAP DIV INV 8SOIC |
| 标准包装： | 100 |
| 类型： | 切换式电容器（充电泵），分配器，反相 |
| 输出数： | 1 |
| 输入电压： | 1.5 V ~ 6 V |
| 频率 - 开关： | 5.5kHz ~ 30kHz |
| 电流 - 输出： | 50mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 包装： | 管件 |
| 供应商设备封装： | 8-SOIC |
| 产品目录页面： | 1339 (CN2011-ZH PDF) |
LTC1046
TYPICAL A PPLICATI
Battery Splitter
S
equal to one half the input voltage. The output voltages are
A common need in many systems is to obtain positive and
negative supplies from a single battery or single power
supply system. Where current requirements are small, the
circuit shown in Figure 10 is a simple solution. It provides
symmetrical positive or negative output voltages, both
both referenced to Pin 3 (output common). If the input
voltage between Pin 8 and Pin 5 is less than 6V, Pin 6
should also be connected to Pin 3, as shown by the
dashed line.
Paralleling for Lower Output Resistance
Additional flexibility of the LTC1046 is shown in Figures 11
and 12. Figure 11 shows two LTC1046s connected in
V B
9V
C1
10 μ F
+
1
2
3
4
LTC1046
CAP + OSC
CAP – V OUT
BOOST V +
GND LV
8
7
6
5
+V B /2
4.5V
REQUIRED FOR V B < 6V
–V B /2
–4.5V
parallel to provide a lower effective output resistance. If,
however, the output resistance is dominated by 1/fC1,
increasing the capacitor size (C1) or increasing the fre-
quency will be of more benefit than the paralleling
circuit shown.
3V ≤ V B ≤ 12V
C2
10 μ F
OUTPUT COMM0N
1046 F10
Figure 10. Battery Splitter
LTC1046
Figure 12 makes use of “stacking” two LTC1046s to
provide even higher voltages. In Figure 12, a negative
voltage doubler or tripler can be achieved depending upon
how Pin 8 of the second LTC1046 is connected, as shown
schematically by the switch.
V +
LTC1046
1
BOOST
V +
8
1
BOOST
V +
8
C1
10 μ F
+
2
3
4
CAP +
GND
CAP –
OSC
LV
V OUT
7
6
5
C1
10 μ F
+
2
3
4
CAP +
GND
CAP –
OSC
LV
V OUT
7
6
5
V OUT = –(V + )
1/4 CD4077
OPTIONAL SYNCHRONIZATION
CIRCUIT TO MINIMIZE RIPPLE
Figure 11. Paralleling for 100mA Load Current
C2
20 μ F
1046 F11
V +
FOR V OUT = –3V +
FOR V OUT = –2V +
1
LTC1046
BOOST
V +
8
C1
10 μ F
1
LTC1046
BOOST
V +
8
10 μ F
+
2
3
CAP +
GND
OSC
LV
7
6
2
3
CAP +
GND
OSC
LV
7
6
4
CAP –
V OUT
5
–(V + )
10 μ F
4
CAP –
V OUT
5
V OUT
10 μ F
1046 F12
Figure 12. Stacking for Higher Voltage
1046fb
8
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