参数资料
| 型号： | LTC1060ACN |
| 厂商： | Linear Technology |
| 文件页数： | 19/20页 |
| 文件大小： | 0K |
| 描述： | IC FILTER BUILDING BLOCK 20-DIP |
| 标准包装： | 18 |
| 滤波器类型： | 通用开关电容器 |
| 频率 - 截止或中心： | 30kHz |
| 滤波器数： | 2 |
| 滤波器阶数： | 4th |
| 电源电压： | ±2.37 V ~ 5 V |
| 安装类型： | 通孔 |
| 封装/外壳： | 20-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 20-PDIP |
| 包装： | 管件 |
8
LTC1060
1060fb
internal op amps, as well as the reference point of all the
internal switches are connected to the AGND pin. Because
of this, a “clean” ground is recommended.
fCLK/f0 Ratio
The fCLK/f0 reference of 100:1 or 50:1 is derived from the
filter center frequency measured in mode 1, with a Q = 10
and VS = ±5V. The clock frequencies are, respectively,
500kHz/250kHz for the 100:1/150:1 measurement. All the
curves shown in the Typical Performance Characteristics
section are normalized to the above references.
Graphs 1 and 2 in the Typical Performance Characteristics
show the (fCLK/f0) variation versus values of ideal Q. The
LTC1060 is a sampled data filter and it only approximates
continuous time filters. In this data sheet, the LTC1060 is
treated in the frequency domain because this approxima-
tion is good enough for most filter applications. The
LTC1060 deviates from its ideal continuous filter model
when the (fCLK/f0) ratio decreases and when the Q’s are
low. Since low Q filters are not selective, the frequency
domain approximation is well justified. In Graph 15 the
LTC1060 is connected in mode 3 and its ( fCLK/f0) ratio is
adjusted to 200:1 and 500:1. Under these conditions, the
filter is over-sampled and the (fCLK/f0) curves are nearly
independent of the Q values. In mode 3, the ( fCLK/f0) ratio
typically deviates from the tested one in mode 1 by ±0.1%.
f0 x Q Product Ratio
This is a figure of merit of general purpose active filter
building blocks. The f0 x Q product of the LTC1060
depends on the clock frequency, the power supply volt-
ages, the junction temperature and the mode of operation.
At 25°C ambient temperature for ±5V supplies, and
for clock frequencies below 1MHz, in mode 1 and its
derivatives, the f0 x Q product is mainly limited by the
desired f0 and Q accuracy. For instance,from
Graph 4 at 50:1 and for fCLK below 800kHz, a predictable
ideal Q of 400 can be obtained. Under this condition, a
respectable f0 x Q product of 6.4MHz is achieved. The
16kHz center frequency will be about 0.22% off from the
tested value at 250kHz clock (see Graph 1). For the same
clock frequency of 800kHz and for the same Q value of
400, the f0 x Q product can be further increased if the
APPLICATIO S I FOR ATIO
WU
UU
clock-to-center frequency is lowered below 50:1. In mode
1c with R6 = 0 and R6 = ∞, the (fCLK/f0) ratio is 50/√2. The
f0 x Q product can now be increased to 9MHz since, with
the same clock frequency and same Q value, the filter can
handle a center frequency of 16kHz x √2.
For clock frequencies above 1MHz, the f0 x Q product is
limited by the clock frequency itself. From Graph 4 at
±7.5V supply, 50:1 and 1.4MHz clock, a Q of 5 has about
8% error; the measured 28kHz center frequency was
skewed by 0.8% with respect to the guaranteed value at
250kHz clock. Under these conditions, the f0 x Q product
is only 140kHz but the filter can handle higher input signal
frequencies than the 800kHz clock frequency, very high Q
case described above.
Mode 3, Figure 11, and the modes of operation where R4
is finite, are “slower” than the basic mode 1. This is shown
in Graph 16 and 17. The resistor R4 places the input op
amp inside the resonant loop. The finite GBW of this op
amp creates an additional phase shift and enhances the Q
value at high clock frequencies. Graph 16 was drawn with
a small capacitor, CC, placed across R4 and as such, at VS
= ±5V, the (1/2πR4CC) = 2MHz. With VS = ±2.5V the (1/
2πR4CC) should be equal to 1.4MHz. This allows the Q
curve to be slightly “flatter” over a wider range of clock
frequencies. If, at ±5V supply, the clock is below 900kHz
(or 400kHz for VS = ±2.5V), this capacitor, CC, is not needed.
For Graph 25, the clock-to-center frequency ratios are
altered to 70.7:1 and 35.35:1. This is done by using mode
1c with R5 = 0, Figure 7, or mode 2 with R2 = R4 = 10k.
The mode 1c, where the input op amp is outside the main
loop, is much faster. Mode 2, however, is more versatile.
At 50:1, and for TA = 25°C the mode 1c can be tuned for
center frequencies up to 30kHz.
Output Noise
The wideband RMS noise of the LTC1060 outputs is nearly
independent from the clock frequency, provided that the
clock itself does not become part of the noise. The LTC1060
noise slightly decreases with ±2.5V supply. The noise at
the BP and LP outputs increases for high Q’s. Table 2
shows typical values of wideband RMS noise. The num-
bers in parentheses are the noise measurement in mode 1
with the SA/B pin shorted to V– as shown in Figure 25.
相关PDF资料 |
PDF描述 |
|---|---|
| LTC1061ACN#PBF | IC FILTER BUILDNG BLK TRPL 20DIP |
| LTC1062CSW#TRPBF | IC FILTR 5TH ORDR LOWPASS 16SOIC |
| LTC1063CSW#TRPBF | IC FILTR 5TH ORDER LOWPASS16SOIC |
| LTC1064-1ACN#PBF | IC FILTR 8TH ORDR LOWPASS 14-DIP |
| LTC1064-2CSW#TRPBF | IC FILTR 8TH ORDR LOWPASS 16SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LTC1060ACN#PBF | 功能描述:IC FILTER BUILDING BLOCK 20-DIP RoHS:是 类别:集成电路 (IC) >> 接口 - 滤波器 - 有源 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 滤波器类型:连续时间，带通低通 频率 - 截止或中心:150kHz 滤波器数:4 滤波器阶数:8th 电源电压:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) |
| LTC1060AM | 制造商:LINER 制造商全称:Linear Technology 功能描述:Universal Dual Filter Building Block |
| LTC1060AMJ | 制造商:LINER 制造商全称:Linear Technology 功能描述:Universal Dual Filter Building Block |
| LTC1060C | 制造商:LINER 制造商全称:Linear Technology 功能描述:Universal Dual Filter Building Block |
| LTC1060CDW | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog IC |
发布紧急采购，3分钟左右您将得到回复。