参数资料
型号: LTC1062CN8
厂商: Linear Technology
文件页数: 12/16页
文件大小: 0K
描述: IC FILTER 5TH ORDER LOWPASS 8DIP
标准包装: 50
滤波器类型: 巴特沃斯,低通开关电容器
频率 - 截止或中心: 20kHz
滤波器数: 1
滤波器阶数: 5th
电源电压: ±8V,5V
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
5
LTC1062
1062fd
8
7
6
5
1
2
3
4
SWITCHED
CAPACITOR
NETWORK
CLOCK GEN
÷ 1, 2, 4
OSC
BOUT
OUT
V+
COSC
1062 BD
÷
V
AGND
FB
fCLK
×1
BY CONNECTING PIN 4 TO V+, AGND OR V, THE
OUTPUT FREQUENCY OF THE INTERNAL CLOCK
GENERATOR IS THE OSCILLATOR FREQUENCY DI-
VIDED BY 1, 2, 4. THE (fCLK/fC) RATIO OF 100:1 IS
WITH RESPECT TO THE INTERNAL CLOCK GENERA-
TOR OUTPUT FREQUENCY. PIN 5 CAN BE DRIVEN
WITH AN EXTERNAL CMOS LEVEL CLOCK. THE
LTC1062 CAN ALSO BE SELF-CLOCKED BY CON-
NECTING AN EXTERNAL CAPACITOR (COSC) TO
GROUND (OR TO VIF COSC IS POLARIZED). UNDER
THIS CONDITION AND WITH ±5V SUPPLIES, THE
INTERNAL OSCILLATOR FREQUENCY IS:
fOSC 140kHz [33pF/(33pF + COSC)]
AC TEST CIRCUIT
FB
AGND
V
DIVIDER
RATIO
BOUT
OUT
V+
COSC
1
2
3
4
8
7
6
5
LTC1062
0.1F
MEASURED
OUTPUT
7
4
8
1
6
0.1F
1062 F01
C = 0.01F
VIN
R = 25.8k
50
5V
–5V
2
3
–5V
5V
fCLK = 100kHz
5V
V= –5V
R′
+
LTC1052
1
2πRC
FOR BEST MAX FLAT APPROXIMATION,
THE INPUT RC SHOULD BE SUCH AS:
A 0.5k RESISTOR, R′, SHOULD BE USED IF
THE BIPOLAR EXTERNAL CLOCK IS APPLIED
BEFORE THE POWER SUPPLIES TURN ON
1
1.63
fCLK
100
=
For Adjusting Oscillator Frequency, Insert a 50k Pot in Series with COSC. Use Two Times Calculated COSC
Figure 1
BLOCK DIAGRA
W
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