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参数资料
| 型号： | LTC1064-1CN |
| 厂商： | Linear Technology |
| 文件页数： | 5/8页 |
| 文件大小： | 0K |
| 描述： | IC FILTR 8TH ORDR LOWPASS 14-DIP |
| 标准包装： | 25 |
| 滤波器类型： | 考尔，低通开关电容器 |
| 频率 - 截止或中心： | 20kHz |
| 滤波器数： | 1 |
| 滤波器阶数： | 8th |
| 电源电压： | ±2.37 V ~ 8 V |
| 安装类型： | 通孔 |
| 封装/外壳： | 14-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 14-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 1324 (CN2011-ZH PDF) |
LTC1064-1
5
10641fa
operation both pins should be tied to one half supply
(Figure 2). Also Pin 8 and Pin 10, although they are not
internally connected should be tied to analog ground or
system ground. This improves the clock feedthrough
performance.
V+, V– (Pins 4, 12): The V+ and V– pins should be
bypassed with a 0.1F capacitor to an adequate analog
ground. Low noise, nonswitching power supplies are
recommended.
To avoid latchup when the power supplies
exhibit high turn-on transients, a 1N5817 Schottky diode
should be added from the V+ and V– pins to ground
(Figure 1).
INV A, R(h, I) (Pins 7, 14): A very short connection
between Pin 14 and Pin 7 is recommended. This connec-
tion should be preferably done under the IC package. In a
UU
U
PI FU CTIO S
breadboard, use a one inch, or less, shielded coaxial cable;
the shield should be grounded. In a PC board, use a one
inch trace or less; surround the trace by a ground plane.
NC (Pins 8, 10): The “no connection” pins preferably
should be grounded.
fCLK (Pin 11): For ±5V supplies the logic threshold level is
1.4V. For ±8V and 0V to 5V supplies the logic threshold
levels are 2.2V and 3V respectively. The logic threshold
levels vary ±100mV over the full military temperature
range. The recommended duty cycle of the input clock is
50% although for clock frequencies below 500kHz the
clock “on” time can be as low as 200ns. The maximum
clock frequency for ±5V supplies is 4MHz. For ±7V sup-
plies and above, the maximum clock frequency is 5MHz.
Do not allow the clock levels to exceed the power supplies.
For clock level shifting (see Figure 3).
Figure 1. Using Schottky Diodes to Protect
the IC from Power Supply Spikes
Figure 2. Single Supply Operation. If Fast Power Up
or Down Transients are Expected, Use a 1N5817
Schottky Diode Between Pin 4 and Pin 5.
Figure 3. Level Shifting the Input T2L Clock
for Single Supply Operation, V+ >6V.
Figure 4. Buffering the Filter Output. The Buffer Op Amp
Should Not Share the LTC1064-1 Power Lines.
LTC1064-1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
0.1F
VOUT
–
+
V–
V+
POWER SOURCE
10k
1064 F04
RECOMMENDED OP AMPS:
LT1022, LT318, LT1056
COMP2*
V–
fCLK
NC
VOUT
NC
INV C
VIN
AGND
V+
AGND
COMP1*
R(h, I)
INV A
VIN
LTC1064-1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
1064 F03
0.1F
5k
2.2k
5k
5k 1
F
T2L
LEVEL
V+
R(h, I)
COMP2*
V–
fCLK
NC
VOUT
NC
INV C
VIN
AGND
V+
AGND
COMP1*
INV A
VOUT
VIN
LTC1064-1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+
V–
1064 F01
0.1F
1N5817
R(h, I)
COMP2*
V–
fCLK
NC
VOUT
NC
INV C
VIN
AGND
V+
AGND
COMP1*
INV A
VOUT
VIN
LTC1064-1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V+= 15V
0V TO 10V
1064 F02
0.1F
5k
V+/2
R(h, I)
COMP2*
V–
fCLK
NC
VOUT
NC
INV C
VIN
AGND
V+
AGND
COMP1*
INV A
VOUT
VIN
TYPICAL APPLICATIO S
U
(Pin Numbers Refer to the 14-Pin Package)
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