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参数资料
| 型号： | LTC1235CSW#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC MPU SUPERVISRY CIRCUIT 16SOIC |
| 标准包装： | 1,000 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极，开路漏极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 4.65V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
LTC1235
PIN FUNCTIONS
V BATT (Pin 1): Backup battery input. When V CC falls below
V BATT , the status of the BACKUP pin stored in the Memory
Logic controls M2. If the status is high, auxiliary power,
connected to V BATT is delivered to V OUT through M2. If the
status is low, the Memory Logic keeps M2 off and V OUT
is in Battery Saving Mode. If backup battery or auxiliary
power is not used, V BATT should be connected to GND.
V OUT (Pin 2): Voltage output for backed up memory. By-
pass with a capacitor of 0.1μF or greater. During normal
operation, V OUT obtains power from V CC through an NMOS
power switch, M1, which can deliver up to 50mA and has a
typical on resistance of 5Ω. When V CC is lower than V BATT ,
the status of the BACKUP pin stored in Memory Logic
controls M2. If the status is high, the Memory Logic turns
on M2 and V OUT is internally switched to V BATT through
M2. If the status is low, the Memory Logic keeps M2 off
and V OUT is in Battery Saving Mode. If V OUT and V BATT
are not used, connect V OUT to V CC .
V CC (Pin 3): +5V supply input. The V CC pin should be
bypassed with a 0.1μF capacitor.
GND (Pin 4): Ground pin.
BATT ON (Pin 5): Battery on logic output from comparator
C2. BATT ON goes low when V OUT is internally connected
to V CC . The output typically sinks 35mA and can provide
base drive for an external PNP transistor to increase the
output current above the 50mA rating of V OUT . BATT ON
goes high when V CC falls below V BATT , if the status of the
BACKUP pin stored in Memory Logic is high and V OUT is
switched to V BATT .
LOW LIN E (Pin 6): Logic output from comparator C1.
LOW LINE indicates a low line condition at the V CC input.
When V CC falls below the reset voltage threshold (4.65V
typically), LOW LINE goes low. As soon as V CC rises above
the reset voltage threshold, LOW LINE returns high (see
Figure 1). LOW LINE goes low when V CC drops below V BATT
(see Table 1).
PB RST (Pin 7): Logic input for direct connection to a push-
button. The push-button reset input requires an active low
signal. Internally, this input signal is debounced and timed
for a minimum of 40ms. When this condition is satis?ed,
the reset pulse generator forces RESET to active low. The
RESET signal will remain active low for a minimum of 140ms
6
from the moment the push-button reset input is released
from logic low level. Pulled to V CC with 60k.
Backup (Pin 8): Logic input to control the PMOS switch,
M2, when V CC is lower than V BATT . While V CC is falling
through the reset voltage threshold, the status of the
BACKUP pin (logic low or logic high) is latched in Memory
Logic and used to turn on or off M2 when V CC is below
V BATT . If the latched status of the BACKUP pin is high,
the Memory Logic turns on M2 when V CC falls to 50mV
greater than V BATT . If the latched status of the BACKUP
pin is low, the Memory Logic keeps M2 off even after V CC
falls below V BATT . If the BACKUP pin is left ?oating it will
be pulled high by an internal pullup and the LTC1235 will
provide battery backup when V CC falls.
PFI (Pin 9): Power Failure Input. PFI is the noninverting
input to the Power Fail Comparator, C3. The inverting input
is internally connected to a 1.3V reference. The Power
Failure Output remains high when PFI is above 1.3V and
goes low when PFI is below 1.3V. Connect PFI to GND or
V OUT when C3 is not used.
PFO (Pin 10): Power Failure Output from C3. PFO remains
high when PFI is above 1.3V and goes low when PFI is
below 1.3V. When V CC is lower than V BATT , C3 is shut
down and PFO is forced low.
WDI (Pin 11): Watchdog Input, WDI, is a three level
input. Driving WDI either high or low for longer than the
watchdog time-out period, forces both RESET and WDO
low. Floating WDI disables the Watchdog Timer. The timer
resets itself with each transition of the Watchdog Input
(see Figure 11).
CE OUT (Pin 12): Logic output from the Chip Enable gating
circuit. When V CC is above the reset voltage threshold, CE
OUT is a buffered replica of CE IN. When V CC is below
the reset voltage threshold CE OUT is forced high (see
Figure 6).
CE IN (Pin 13): Logic input to the Chip Enable gating cir-
cuit. CE IN can be derived from microprocessor’s address
line and/or decoder output. See Applications Information
Section and Figure 6 for additional information.
WDO (Pin 14): Watchdog logic output. When the watch-
dog input remains either high or low for longer than the
watchdog time-out period, WDO goes low. WDO is set
1235fa
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