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参数资料
| 型号： | LTC1326CMS8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 8/16页 |
| 文件大小： | 0K |
| 描述： | IC PREC TRPL SUPPLY MONITR 8MSOP |
| 标准包装： | 50 |
| 类型： | 多压监控器 |
| 监视电压数目： | 3 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 3.118V，4.725V，可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
LTC1326/LTC1326-2.5
TI I G DIAGRA S
V CC Monitor Timing
Push-Button Reset Function Timing
V CCX
V RTX
t RST
PBR
t < t PB
t DB
t PB
t RST
RST
RST
1326 /2.5 TD01
t SRST
APPLICATIO S I FOR ATIO
SRST
1326 /2.5 TD02
Operation
The LTC1326/LTC1326-2.5 are micropower, high accu-
racy triple supply monitoring circuits. The parts have two
basic functions: generation of a reset when power sup-
plies are out of range, and generation of reset or a “soft”
reset when the PBR pin is pulled low.
Supply Monitoring
All three V CC inputs must be above predetermined
thresholds for 200ms before the reset output is released.
The parts will assert reset during power-up, power-down
and brownout conditions on any one or more of the V CC
inputs.
On power-up, either the V CC5 or V CC3 pin on the LTC1326,
or the V CC25 or V CC3 pin on the LTC1326-2.5, can power
the drive circuits for the RST pin. This ensures that RST
will be low when V CC5 , V CC25 or V CC3 reaches 1V. As long
as any one of the V CC inputs is below its predetermined
threshold, RST will stay a logic low. Once all of the V CC
inputs rise above their thresholds, an internal timer is
started and RST is released after 200ms. The RST pin
outputs the inverted state of what is seen on RST pin.
RST is reasserted whenever any one of the V CC inputs
drops below its predetermined threshold and remains
asserted until 200ms after all of the V CC inputs are above
their thresholds.
On power-down, once any of the V CC inputs drop below
its threshold, RST is held at a logic low. A logic low of 0.4V
is guaranteed until V CC3 and V CC5 on the LTC1326 or V CC3
The three internal precision voltage comparators have
response times that are typically 13 μ s. This slow re-
sponse time helps prevent mistriggering due to tran-
sients on each of the V CC inputs. The part’s ability to
suppress transients can be improved by bypassing each
of the V CC inputs with a 0.1 μ F capacitor to ground.
Push-Button Reset
The parts provide a push-button reset input pin. The PBR
input has an internal pull-up current source to V CC3 . If the
PBR pin is not used it can be left floating.
When the PBR is pulled low for less than t PB ( ≈ 2 sec), a
narrow (100 μ s typ) soft reset pulse is generated on the
SRST output pin after the button is released. The push-
button circuitry contains an internal debounce counter
which delays the output of the soft reset pulse by typically
20ms. This pin can be OR-tied to the RST pin and issue
what is called a “soft” reset. The SRST thereby resets the
microprocessor without interrupting the DRAM refresh
cycle. In this manner DRAM information remains undis-
turbed. Alternatively, SRST may be monitored by the
processor to initiate a software-controlled reset.
When the PBR pin is held low for longer than t PB ( ≈ 2 sec),
a standard reset is generated on the RST and RST pins.
Once the 2 second period has elapsed, a reset signal is
produced by the push-button logic, thereby clearing the
reset counter. Once the button is released, the reset
counter begins counting the reset period (200ms nomi-
nal). Consequently, the reset outputs remain asserted for
approximately 200ms after the button is released.
and V CC25 on the LTC1326-2.5 drop below 1V.
132625fc
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