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参数资料
| 型号： | LTC1326CS8#TR |
| 厂商： | Linear Technology |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC MONITOR TRPL SPPLY PREC 8SOIC |
| 标准包装： | 2,500 |
| 类型： | 多压监控器 |
| 监视电压数目： | 3 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 3.118V，4.725V，可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
LTC1326/LTC1326-2.5
TYPICAL PERFOR A CE CHARACTERISTICS
225
220
215
210
205
200
195
190
Reset Pulse Width
vs Temperature
112.5
110.0
107.5
105.0
102.5
100.0
97.5
95.0
“Soft” Reset Pulse Width
vs Temperature
2.25
2.20
2.15
2.10
2.05
2.00
1.95
1.90
PBR Assertion Time to Reset
vs Temperature
– 60 – 40 – 20
0
20
40
60
80
100
– 60 – 40 – 20
0
20
40
60
80
100
– 60 – 40 – 20
0
20
40
60
80
100
TEMPERATURE ( ° C)
PI N FU N CTIO N S
1326 /2.5 G13
TEMPERATURE ( ° C)
1326 /2.5 G14
TEMPERATURE ( ° C)
1326 /2.5 G15
V CC3 (Pin 1): 3.3V Sense Input and Power Supply Pin for
the IC. Bypass to ground with ≥ 0.1 μ F ceramic capacitor.
V CC5 (Pin 2) (LTC1326): 5V Sense Input. Used as gate
drive for the RST output FET when the voltage on V CC3 is
less than the voltage on V CC5 . If unused, it can be tied to
V CC3 (see Dual and Single Supply Monitor Operation in
the Applications Information section).
V CC25 (Pin 2) (LTC1326-2.5): 2.5V Sense Input. Used as
gate drive for RST output FET when the voltage on V CC3
is less than the voltage on V CC25 . If unused, it can be tied
to V CC3 .
V CCA (Pin 3): 1V Sense, High Impedance Input. Can be
used as a logic input with a 1V threshold. If unused, it can
be tied to either V CC3 or V CC25 .
GND (Pin 4): Ground.
RST (Pin 5): Reset Logic Output. Active high CMOS logic
output, drives high to V CC3 , buffered complement of RST.
An external pull-down on the RST pin will drive this pin
high.
RST (Pin 6): Reset Logic Output. Active low, open-drain
logic output with weak pull-up to V CC3 . Can be pulled up
greater than V CC3 when interfacing to 5V logic. Asserted
when one or more of the supplies are below trip
thresholds and held for 200ms after all supplies become
valid. Also asserted after PBR is held low for more than
2 seconds and for an additional 200ms after PBR is
released.
SRST (Pin 7): Soft Reset. Active low, open-drain logic
output with weak pull-up to V CC3 . Can be pulled up
greater than V CC3 when interfacing to 5V logic. Asserted
for 100 μ s after PBR is held low for less than 2 seconds
and released.
PBR (Pin 8): Push-Button Reset. Active low logic input
with weak pull-up to V CC3 . Can be pulled up greater than
V CC3 when interfacing to 5V logic. When asserted for less
than 2 seconds, outputs a soft reset 100 μ s pulse on the
SRST pin. When PBR is asserted for greater than 2
seconds, the RST output is forced low and remains low
until 200ms after PBR is released.
132625fc
6
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