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参数资料
| 型号： | LTC1329CS8-50#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/8页 |
| 文件大小： | 0K |
| 描述： | IC D/A CONV 8BIT MICROPWR 8-SOIC |
| 标准包装： | 100 |
| 位数： | 8 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 840µW |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
| 输出数目和类型： | 1 电流，单极 |
| 采样率（每秒）： | * |
| 产品目录页面： | 1352 (CN2011-ZH PDF) |
7
LTC1329-10/
LTC1329-50/LTC1329A-50
APPLICATIONS INFORMATION
WU
U
Standard 3-Wire Mode (Figure 3)
Refer to the Serial Interface Operating Sequence in Figure
1. When operating in 3-wire mode, the LTC1329-10/
LTC1329-50/LTC1329A-50 will interface directly with most
standard 3- or 4-wire serial interface systems. The clock
(CLK) input synchronizes the data transfer with each input
bit captured at the rising edge of CLK and each output data
bit shifted out through DOUT at the falling edge. A falling
edge at CS initiates the data transfer and brings the DOUT
pin out of three-state. The serial 8-bit data representing the
new DAC setting is shifted into the DIN pin. Simulta-
neously, the previous DAC setting is shifted out of the
DOUT pin. After the new data is shifted in, a rising edge at
CS transfers the data from the input shift register into the
DAC register. The DAC output assumes the new value and
the DOUT pin returns to a high-impedance state.
IOUT = (B7 B6 B5 B4 B3 B2 B1 B0)IFULLSCALE/255
1
2
SHDN
CLK
CS
DIN
DOUT
8
7
DOUT
DIN
IOUT
VCC
SHDN
CLK
LTC1329
GND
CS
1329 F03
IOUT
3
4
6
5
VCC
0.1
F
DIN AND DOUT CAN BE TIED TOGETHER
FOR HALF DUPLEX DATA TRANSFER
Figure 3. 3-Wire Mode; Serial Interface
(3-Wire Control by CS, CLK and DIN)
1-Wire Interface (Pulse Mode, Figure 4)
In 1-wire pulse mode, each rising edge at CLK increments
the upper six bits of the DAC register by one count. When
incramented beyond 11111100B, the counter rolls over
and sets the DAC to the minimum value (00000000B). In
this way, a single pulse applied to CLK increases the DAC
output by a single 4-LSB step and 63 pulses decrease the
DAC output by one step. The last two LSBs are always zero
in pulse mode.
IOUT = (B7 B6 B5 B4 B3 B2 0 0)IFULLSCALE/255
To configure the LTC1329-10/LTC1329-50/LTC1329A-50
in 1-wire pulse mode, tie both the CS and DIN pins to VCC.
1
2
SHDN
CLK
8
7
DOUT
DIN
IOUT
VCC
SHDN
CLK
LTC1329
GND
CS
1329 F04
IOUT
3
4
6
5
0.1
F
Figure 4. Pulse Mode: Increment Only
(1-Wire Control by CLK)
2-Wire Interface (Pulse Mode, Figure 5)
In 2-wire pulse mode, a logic HIGH at UP/DN programs the
DAC register to increment and each rising edge at CLK
increments the upper six bits of the register by one count.
Similarly, a logic LOW at UP/DN set the DAC register to
decrement and a rising edge at CLK decrements the upper
six bits of the register by one count. Each count in 2-wire
mode changes the DAC output by a single four LSB step.
The DAC register stops incramenting at 11111100B and
stops decrementing at 00000000B and will not roll over in
2-wire pulse mode. The last two LSBs are always zero in
pulse mode.
IOUT = (B7 B6 B5 B4 B3 B2 0 0)IFULLSCALE/255
To configure the LTC1329-10/LTC1329-50/LTC1329A-50
in 2-wire pulse mode, tie CS to VCC and bring the UP/DN
pin low at least once during power-up.
1
2
SHDN
CLK
UP/DN
8
7
DOUT
DIN
IOUT
VCC
SHDN
CLK
LTC1329
GND
CS
1329 TA04
IOUT
3
4
6
5
0.1
F
Figure 5. Pulse Mode; Increment/Decrement
(2-Wire Control by CLK and UP/DN)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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