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参数资料
| 型号： | LTC1408IUH-12#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 18/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 600KSPS 32-QFN |
| 标准包装： | 73 |
| 位数： | 12 |
| 采样率（每秒）： | 600k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 15mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 管件 |
| 输入数目和类型： | 12 个单端，单极；12 个单端，双极；6 个差分，单极；6 个差分，双极 |
| 产品目录页面： | 1346 (CN2011-ZH PDF) |
| 配用： | DC887A-ND - BOARD SAR ADC LTC1408 |
7
LTC1408-12
140812f
UU
U
PI FU CTIO S
SDO (Pin 1): Three-State Serial Data Output. Each set of
six output data words represent the six analog input
channels at the start of the previous conversion. Data for
CH0 comes out first and data for CH5 comes out last. Each
data word comes out MSB first.
OGND (Pin 2): Ground Return for SDO Currents. Connect
to the solid ground plane.
OVDD (Pin 3): Power Supply for the SDO Pin. OVDD must
be no more than 300mV higher than VDD and can be
brought to a lower voltage to interface to low voltage logic
families. The unloaded high state at SDO is at the potential
of OVDD.
CH0+ (Pin 4): Non-Inverting Channel 0. CH0+ operates
fully differentially with respect to CH0– with a 0V to 2.5V,
or
±1.25V differential swing and a 0V to VDD absolute
input range.
CH0– (Pin 5): Inverting Channel 0. CH0– operates fully
differentially with respect to CH0+ with a –2.5V to 0V,
or
±1.25V differential swing and a 0V to VDD absolute
input range.
GND (Pins 6, 9, 12, 13, 16, 19): Analog Grounds. These
ground pins must be tied directly to the solid ground plane
under the part. Analog signal currents flow through these
connections.
CH1+ (Pin 7): Non-Inverting Channel 1. CH1+ operates
fully differentially with respect to CH1– with a 0V to 2.5V,
or
±1.25V differential swing and a 0V to VDD absolute
input range.
CH1– (Pin 8): Inverting Channel 1. CH1– operates fully
differentially with respect to CH1+ with a –2.5V to 0V,
or
±1.25V differential swing and a 0V to VDD absolute
input range.
CH2+ (Pin 10): Non-Inverting Channel 2. CH2+ operates
fully differentially with respect to CH2– with a 0V to 2.5V,
or
±1.25V differential swing and a 0V to VDD absolute
input range.
CH2– (Pin 11): Inverting Channel 2. CH2– operates fully
differentially with respect to CH2+ with a –2.5V to 0V, or
±1.25V differential swing and a 0V to VDD absolute
input range.
CH3+ (Pin 14): Non-Inverting Channel 3. CH3+ operates
fully differentially with respect to CH3– with a 0V to 2.5V,
or
±1.25V differential swing and a 0V to VDD absolute
input range.
CH3– (Pin 15): Inverting Channel 3. CH3– operates fully
differentially with respect to CH3+ with a –2.5V to 0V, or
±1.25V differential swing and a 0V to VDD absolute
input range.
CH4+ (Pin 17): Non-Inverting Channel 4. CH4+ operates
fully differentially with respect to CH4– with a 0V to 2.5V,
or
±1.25V differential swing and a 0V to VDDabsolute input
range.
CH4– (Pin 18): Inverting Channel 4. CH4– operates fully
differentially with respect to CH4+ with a –2.5V to 0V, or
±1.25V differential swing and a 0V to VDD absolute input
range.
CH5+ (Pin 20): Non-Inverting Channel 5. CH5+ operates
fully differentially with respect to CH5– with a 0V to 2.5V,
or
±1.25V differential swing and a 0V to VDDabsolute input
range.
CH5– (Pin 21): Inverting Channel 5. CH5– operates fully
differentially with respect to CH5+ with a –2.5V to 0V, or
±1.25V differential swing and a 0V to VDD absolute input
range.
GND (PIN 22): Analog Ground for Reference. Analog
ground must be tied directly to the solid ground plane
under the part. Analog signal currents flow through this
connection. The 10
F reference bypass capacitor should
be returned to this pad.
VREF (Pin 23): 2.5V Internal Reference. Bypass to GND
and a solid analog ground plane with a 10
F ceramic
capacitor (or 10
F tantalum in parallel with 0.1F ce-
ramic). Can be overdriven by an external reference voltage
between 2.55V and VDD, VCC.
VCC (Pin 24): 3V Positive Analog Supply. This pin supplies
3V to the analog section. Bypass to the solid analog
ground plane with a 10
F ceramic capacitor (or 10F
tantalum) in parallel with 0.1
F ceramic. Care should be
taken to place the 0.1
F bypass capacitor as close to
Pin 24 as possible. Pin 24 must be tied to Pin 25.
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