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参数资料
| 型号： | LTC1409CSW#TR |
| 厂商： | Linear Technology |
| 文件页数： | 19/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 800KSPS SMPL 28SOIC |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 800k |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 120mW |
| 电压电源： | 双 ± |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，双极；1 个差分，双极 |
8
LTC1409
APPLICATIONS INFORMATION
WU
U
CONVERSION DETAILS
The LTC1409 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit
(LSB). Referring to Figure 1, the +AIN and –AIN inputs are
connected to the sample-and-hold capacitors (CSAMPLE)
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum delay of 150ns will provide enough time for the
sample-and-hold capacitors to acquire the analog signal.
During the convert phase the comparator zeroing switches
open, putting the comparator into compare mode. The
input switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
differential capacitive DAC. Bit decisions are made by the
high speed comparator. At the end of a conversion, the
differential DACs output balances the +AIN and –AIN input
charges. The SAR contents (a 12-bit data word) which
represents the difference of +AIN and –AIN are loaded into
the 12-bit output latches.
DYNAMIC PERFORMANCE
The LTC1409 has excellent high speed sampling capabil-
ity. FFT (Fast Four Transform) test techniques are used to
test the ADC’s frequency response, distortion and noise at
the rated throughput. By applying a low distortion sine
wave and analyzing the digital output using FFT algorithm,
the ADC’s spectral content can be examined for frequen-
cies outside the fundamental. Figure 2 shows typical
LTC1409 plots.
Figure 1. Simplified Block Diagram
COMP
+CSAMPLE
–CDAC
D11
D0
ZEROING SWITCHES
HOLD
+AIN
–AIN
+CDAC
–CSAMPLE
12
LTC1409 F01
+
–
SAR
OUTPUT
LATCHES
+VDAC
–VDAC
HOLD
Figure 2b. LTC1409 Nonaveraged, 4096 Point FFT,
Input Frequency = 375kHz
FREQUENCY (kHz)
0
AMPLITUDE
(dB)
100
200
300
400
LT1409 F02b
0
–20
–40
–60
–80
–100
–120
50
150
250
350
fSAMPLE = 800kHz
fIN = 375kHz
SFDR = 89dB
SINAD = 72.5dB
Figure 2a. LTC1409 Nonaveraged, 4096 Point FFT,
Input Frequency = 100kHz
FREQUENCY (kHz)
0
AMPLITUDE
(dB)
100
200
300
400
LT1409 F02a
0
–20
–40
–60
–80
–100
–120
50
150
250
350
fSAMPLE = 800kHz
fIN = 97.45kHz
SFDR = 89.1dB
SINAD = 73.1dB
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