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参数资料
| 型号： | LTC1410CSW#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 11/16页 |
| 文件大小： | 0K |
| 描述： | IC A/D CONV 12BIT SAMPLNG 28SOIC |
| 标准包装： | 27 |
| 位数： | 12 |
| 采样率（每秒）： | 1.25M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 230mW |
| 电压电源： | 双 ± |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 管件 |
| 输入数目和类型： | 2 个单端，双极；1 个差分，双极 |
| 产品目录页面： | 1346 (CN2011-ZH PDF) |
4
LTC1410
POWER REQUIRE E TS
W U
The q denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PD
Power Dissipation
160
230
mW
Nap Mode
SHDN = 0V, NAP/SLP = 5V
7.5
12
mW
Sleep Mode
SHDN = 0V, NAP/SLP = 0V
0.01
1
mW
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fSAMPLE(MAX)
Maximum Sampling Frequency
q
1.25
MHz
tCONV
Conversion Time
q
650
750
ns
tACQ
Acquisition Time
q
50
100
ns
tACQ+CONV
Throughput Time
q
800
ns
(Acquisition + Conversion)
t1
CS to RD Setup Time
(Notes 9, 10)
q
0ns
t2
CS
↓ to CONVST↓ Setup Time
(Notes 9, 10)
q
10
ns
t3
NAP/SLP
↓ to SHDN↓ Setup Time
(Notes 9, 10)
q
10
ns
t4
SHDN
↑ to CONVST↓ Wake-Up Time (Note 10)
200
ns
t5
CONVST Low Time
(Notes 10, 11)
q
40
ns
t6
CONVST to BUSY Delay
CL = 25pF
10
ns
q
50
ns
t7
Data Ready Before BUSY
↑
20
35
ns
q
15
ns
t8
Delay Between Conversions
(Note 10)
q
40
ns
t9
Wait Time RD
↓ After BUSY↑
(Note 10)
q
–5
ns
t10
Data Access Time After RD
↓
CL = 25pF
15
25
ns
q
35
ns
CL = 100pF
20
35
ns
q
50
ns
t11
Bus Relinquish Time
820
ns
Commercial
q
25
ns
Industrial
q
30
ns
t12
RD Low Time
q
t10
ns
t13
CONVST High Time
q
40
ns
t14
Aperture Delay of Sample-and-Hold
– 1.5
ns
TI I G CHARACTERISTICS
W U
The q denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from – 0.5LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
Note 11: The falling CONVST edge starts a conversion. If CONVST returns
high at a critical point during the conversion it can create small errors. For
best results ensure that CONVST returns high either within 425ns after the
start of the conversion or after BUSY rises.
Note 12: Signal-to-noise ratio (SNR) is measured at 100kHz and distortion
is measured at 600kHz. These results are used to calculate signal-to-noise
plus distortion (SINAD).
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND, OGND
and AGND wired together unless otherwise noted.
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.
Note 4: When these pin voltages are taken below VSS, they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. These pins are not clamped to VDD.
Note 5: VDD = 5V, VSS = – 5V, fSAMPLE = 1.25MHz, tr = tf = 5ns unless
otherwise specified.
Note 6: Linearity, offset and full-scale specifications apply for a single-
ended +AIN input with – AIN grounded.
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