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参数资料
| 型号： | LTC1415ISW#TR |
| 厂商： | Linear Technology |
| 文件页数： | 6/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 1.25MSPS SMP 28SOIC |
| 标准包装： | 1,000 |
| 位数： | 12 |
| 采样率（每秒）： | 1.25M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 100mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，双极；1 个差分，双极 |
14
LTC1415
APPLICATIONS INFORMATION
WU
U
limitations at high input frequencies (THD = 75dB at
600kHz). The ADC in Figure 10e has a full scale of 2.048V
and a common mode of 2.27V. The reduced signal swing
of this circuit results in improved distortion at higher input
frequencies (THD = 82dB at 600kHz) but with worse
SINAD at low frequencies (SINAD = 70dB at 100kHz).
Full-Scale and Offset Adjustment
Figure 11a shows the ideal input/output characteristics
for the LTC1415. The code transitions occur midway
between successive integer LSB values (i.e., 0.5LSB,
1.5LSB, 2.5LSB,... FS – 1.5LSB, FS – 0.5LSB). The output
is straight binary with 1LSB = FS/4096 = 4.096V/4096
= 1mV.
Figure 11b. Offset and Full-Scale Adjust Circuit
ANALOG
INPUT
LTC1415 F11b
R4
100
R1
100
R3
24k
R2
47k
R8
50k
R7
50k
R5
47k
R6
24k
0.1
F
10
F
5V
+AIN
–AIN
VREF
LTC1415
1
2
3
5
4
AGND
REFCOMP
the output code flickers between 1111 1111 1110 and
1111 1111 1111.
BOARD LAYOUT AND GROUNDING
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1415, a printed circuit board
with ground plane is required. The ground plane under the
ADC area should be as free of breaks and holes as
possible, such that a low impedance path between all ADC
grounds and all ADC decoupling capacitors is provided. It
is critical to prevent digital noise from being coupled to the
analog input, reference or analog power supply lines.
Layout should ensure that digital and analog signal lines
are separated as much as possible. Particular care should
be taken not to run any digital track alongside an analog
signal track.
An analog ground plane separate from the logic system
ground should be established under and around the ADC.
Pin 5 (AGND), Pin 14 and Pin 19 (ADC’s DGND) and all
other analog grounds should be connected to this single
analog ground point. The REFCOMP bypass capacitor and
the DVDD bypass capacitor should also be connected to
this analog ground plane. No other digital grounds should
be connected to this analog ground plane. Low impedance
analog and digital power supply common returns are
essential to low noise operation of the ADC and the foil
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error must be adjusted before full-scale error. Figure 11b
shows the extra components required for full-scale error
adjustment. Zero offset is achieved by adjusting the offset
applied to the – AIN input. For zero offset error apply
0.5mV (i.e., 0.5LSB) at +AIN and adjust the offset at the
–AIN input (R8) until the output code flickers between
0000 0000 0000 and 0000 0000 0001. For full-scale
adjustment, an input voltage of 4.0945V (FS – 1.5LSBs)
is applied to the analog input and R7 is adjusted until
INPUT VOLTAGE (V)
OUTPUT
CODE
LTC1415 F11a
111...111
111...110
111...101
000...010
000...001
000...000
1LSB
FS – 1LSB
Figure 11a. LTC1415 Transfer Characteristics
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