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参数资料
| 型号： | LTC1417IGN#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 32/32页 |
| 文件大小： | 0K |
| 描述： | IC A/D CONV 14BIT SAMPLNG 16SSOP |
| 标准包装： | 100 |
| 位数： | 14 |
| 采样率（每秒）： | 400k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 27.5mW Unipolar; 44mW Bipolar |
| 电压电源： | 双 ± |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 2 个单端，单极；2 个单端，双极；1 个差分，单极；1 个差分，双极 |
| 产品目录页面： | 1346 (CN2011-ZH PDF) |
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9
LTC1417
sn1417 1417fas
CONVERSION DETAILS
The LTC1417 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 14-bit serial output. The ADC is com-
plete with a precision reference and an internal clock. The
control logic provides easy interface to microprocessors
and DSPs (please refer to Digital Interface section for the
data format).
Conversion start is controlled by the CONVST input. At the
start of the conversion, the successive approximation
register (SAR) is reset. Once a conversion cycle has
begun, it cannot be restarted.
During the conversion, the internal differential 14-bit
capacitive DAC output is sequenced by the SAR from the
most significant bit (MSB) to the least significant bit (LSB).
Referring to Figure 1, the AIN+ and AIN– inputs are con-
nected to the sample-and-hold capacitors (CSAMPLE) dur-
ing the acquire phase and the comparator offset is nulled by
the zeroing switches. In this acquire phase, a minimum
delay of 500ns will provide enough time for the sample-
and-hold capacitors to acquire the analog signal. During
the convert phase, the comparator zeroing switches open,
placing the comparator in compare mode. The input
switches connect the CSAMPLE capacitors to ground,
transferring the differential analog input charge onto the
summing junction. This input charge is successively
compared with the binary weighted charges supplied by
the differential capacitive DAC. Bit decisions are made by
the high speed comparator. At the end of a conversion, the
differential DAC output balances the AIN+ and AIN– input
charges. The SAR contents (a 14-bit data word) that
represent the difference of AIN+ and AIN– are output
through the serial pin DOUT.
DC Performance
One way of measuring the transition noise associated with
a high resolution ADC is to use a technique where a DC
signal is applied to the input of the ADC and the resulting
output codes are collected over a large number of conver-
sions. For example in Figure 2, the distribution of output
code is shown for a DC input that has been digitized 4096
times. The distribution is Gaussian and the RMS code
transition is about 0.33LSB.
Figure 1. Simplified Block Diagram
1417 F01
SHIFT
REGISTER
SAR
CDAC
+
CDAC
–
VDAC
–
VDAC
+
–
+
COMP
DOUT
14
HOLD
AIN
+
AIN
–
ZEROING SWITCHES
CSAMPLE
–
CSAMPLE
+
HOLD
SAMPLE
APPLICATIONS INFORMATION
WU
U
CODE
–2
COUNTS
1500
2000
2500
1
1417 F02
1000
500
0
–1
0
2
3000
3500
4000
Figure 2. Histogram for 4096 Conversions
DYNAMIC PERFORMANCE
The LTC1417 has excellent high speed sampling capabil-
ity. FFT (Fast Fourier Transform) test techniques are used
to test the ADC’s frequency response, distortion and
noise performance at the rated throughput. By applying
a low distortion sine wave and analyzing the digital output
using an FFT algorithm, the ADC’s spectral content can be
examined for frequencies beyond the fundamental.
Figure 3 shows a typical LTC1417 FFT plot.
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