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参数资料
| 型号： | LTC1422IN8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/16页 |
| 文件大小： | 197K |
| 描述： | IC CONTROLLER HOT SWAP 8-DIP |
| 标准包装： | 50 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 2.7 V ~ 12 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
7
LTC1422
1422fb
APPLICATIONS INFORMATION
U
U
U
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the board can draw huge
transient currents from the backplane power bus as they
charge up. The transient currents can cause permanent
damage to the connector pins and cause glitches on the
system supply, causing other boards in the system to
reset.
The LTC1422 is designed to turn a boards supply voltage
on and off in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
also provides a system reset signal to indicate when board
supply voltage drops below a programmable voltage.
Power Supply Ramping
The onboard power supply is controlled by placing an
external N-channel pass transistor in the power path
(Figure 1). R1 provides current fault detection and R2
prevents high frequency oscillation. By ramping up the
gate of the pass transistor at a controlled rate, the transient
surge current (I = C " dV/dt) drawn from the main backplane
supply can be limited to a safe value when the board makes
connection.
V
CC
+ 10V
V
CC
1422 F02
t
1
t
2
GATE
V
OUT
SLOPE = 10礎/C1
Figure 2. Supply Turn-On
Figure 3. Supply Monitor Block Diagram
equal to 10礎/C1
(Figure 2), where C1
is the external
capacitor connected between the GATE pin and GND.
The ramp time for the supply is equal to: t = (V
CC
" C1)/
10礎. After the ON pin has been pulled low for more than
40祍, the GATE is immediately pulled to GND.
Voltage Monitor
The LTC1422 uses a 1.232V bandgap reference, precision
voltage comparator and a resistive divider to monitor the
output supply voltage (Figure 3).
Figure 1. Supply Control Circuitry
+
V
CC
SENSE
TIMER
GND
GATE
LTC1422
ON
8
3
4
7
6
C1
C
LOAD
C2
R3
V
OUT
V
CC
Q1
R1
5
2
1422F01
1
FB
RESET
R2
10&
R4
When power is first applied to the chip, the gate of the
N-channel (Pin 6) is pulled low. After the ON pin is held
high for at least one timing cycle, the charge pump is
turned on. The voltage at GATE begins to rise with a slope
+
SENSE
12礎
R4
R3
7
V
CC
V
OUT
V
CC
8
GATE
LTC1422
6
2
FB
Q2
ON
1422 F03
1
5
C2
3
4
C1
C
LOAD
Q1
R1
LOGIC
TIMER
1.232V
REFERENCE
+
COMP 2
礟
RESET
R2
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