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| 型号： | LTC1426IS8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/8页 |
| 文件大小： | 0K |
| 描述： | IC PWM D/A CONV 6BIT DUAL 8-SOIC |
| 标准包装： | 100 |
| 位数： | 6 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 550µW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
| 输出数目和类型： | 2 电压，单极 |
| 采样率（每秒）： | * |
7
LTC1426
TYPICAL APPLICATIONS N
U
microprocessor has “quasi-bidirectional” ports that elimi-
nate additional pull-up resistors to VCC. However, external
pull-up resistors should be used if the microprocessor
doesn’t pull the port pins high during reset.
In pulse mode, each clock pulse applied to the CLK1 or
CLK2 input increments the respective counter by one
count. When the counter increases beyond full scale
(111111B), the counter rolls over and becomes zero scale
(000000B). In this way, a single pulse applied to the CLK1
or CLK2 input increases the respective counter by one
count, and 63 pulses decrease that counter by one count.
Pushbutton Mode
Figure 5 shows how to use the LTC1426 in a typical
pushbutton application. In pushbutton mode, a logic 1
pulse applied to the CLK1 or CLK2 input increments the
respective counter by one count, and stops incrementing
when the counter reaches full scale (111111B). A logic 0
pulse applied to the CLK1 or CLK2 input decrements the
respective counter by one count, and stops decrementing
when the counter reaches zero scale (000000B). An on-
chip debouncing circuit has a debounce time of 12.8ms to
prevent unintended counts with bouncing pushbuttons.
After a time delay of 410ms, the counter will begin to
increment/decrement at a repeat rate of 19.5Hz if the
pushbutton remains pressed.
Care should be taken to avoid running the CLK and PWM
traces close to one another. Since the CLK pins are high
impedance input nodes in pushbutton mode, current
spikes caused by the switching of the PWM outputs
feedthrough via any stray capacitance between PWM and
CLK lines if not properly routed. Use of proper grounding
techniques and spacing of these lines are highly recom-
mended for optimal performance.
Figure 6 shows a dual digitally programmable current
source using the LT
1013 dual precision op amp and two
NPN transistors (2N3904). After the lowpass filter combi-
nation of R1, C1 (R2, C2), its output swings from 0V to
4.93V. In the configuration shown, this voltage will be
forced across the resistor RA1(RA2). If RA1(RA2) is chosen
to be 493
, the output current will range from 0mA at zero
scale to 10mA at full scale. The minimum voltage for VS is
determined by the load resistor RL1 (RL2) and Q1(Q2)’s
VCESAT voltage. With a load resistor of 50, the voltage
source can be as low as 5V.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
Figure 6. Dual Digitally Programmable Current Source
1
2
3
4
8
7
6
5
CLK1
CLK2
GND
PWM1
SHDN
VCC
VREF
PWM2
LTC1426
PWM1
1426 F05
PWM2
PWM1/PWM2: 0V TO 0.985(VREF)
0.1
F
VREF
0V TO 5.5V
VCC
2.7V TO 5.5V
VCC
2.7V TO 5.5V
SHDN
DOWN
UP
RR
LIMITING RESISTOR R PREVENTS SHORTING OF VCC AND GND WHEN BOTH
BUTTONS ARE SIMULTANEOUSLY PUSHED. THIS RESISTOR CAN BE PLACED
EITHER IN THE VCC OR GND LEG AND THIS DETERMINES THE FUNCTION WHEN
BOTH BUTTONS ARE PUSHED. VALUE OF R < 50k
Figure 5. Pushbutton Mode Interface
1
2
3
4
8
7
6
5
CLK1
CLK2
GND
PWM1
SHDN
VCC
VREF
PWM2
P1.0
P1.1
LTC1426
1
2
3
4
8
7
6
5
OUT A
–IN A
+IN A
V –
V +
OUT B
– IN B
+ IN B
LT1013
MPU
(e.g. 8051)
0.1
F
0.1
F
RA1
493
R1
10k
5V
10V
VS
C1
0.1
F
SHDN
2N3904
R2
10k
C2
0.1
F
1426 F06
RL1
IOUT1/IOUT2: 0mA TO 10mA
RL1/RL2: <50
VS: 5V TO 30V
RL2
RA2
493
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