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参数资料
| 型号： | LTC1427CS8-50#TRPBF |
| 厂商： | Linear Technology |
| 文件页数： | 7/8页 |
| 文件大小： | 0K |
| 描述： | IC D/A CONV 10BIT W/SMBUS 8-SOIC |
| 标准包装： | 2,500 |
| 位数： | 10 |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 550µW |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电流，单极 |
| 采样率（每秒）： | * |
7
LTC1427-50
APPLICATIONS INFORMATION
WU
U
Data Byte
mand code and data byte are defined with the following
format:
7
6
5
4
3
2
10
765
4
3210
SHDN X
X X
X
X D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
SHDN: 0 for Normal Operation, 1 for Shutdown
D9 to D0: DAC Data Bits, D9 is the Most Significant Bit
START and STOP Conditions
At the beginning of any SMBus communication, the mas-
ter must transmit a START condition by switching the SDA
from high to low while SCL is high. When a master has
finished communicating with a slave device, a STOP
condition is issued by switching the SDA from low to
high while SCL is high. The SMBus is then free for
communication with another SMBus slave device.
Early STOP Conditions
The LTC1427-50 recognizes a STOP condition at any point
in the SMBus communication sequence. If the STOP
occurs prematurely before the data byte is acknowledged
in the Write Byte protocol, the DAC output current value is
not updated; otherwise internal register C is updated with
the new data and the DAC output current changes
correspondingly.
Command Byte
LTC1427-50 Used to Null Op Amp’s Offset Voltage
TYPICAL APPLICATIONS
U
1
2
3
4
8
7
6
5
SHDN
1427 TA03
TO
SMBUS
HOST
VCC
VIN
VOUT
V–
RF
R2
100
R1
600k
LTC1427-50
SHDN
AD1
AD0
GND
VCC
IOUT
SCL
SDA
–
+
LT1006
RIN
TRIM RANGE =
±(0.5)(IFULL SCALE)(R2)
R1 =
V–
(0.5)(IFULL SCALE)
The Slave Address
The LTC1427-50 can respond to one of four 7-bit
addresses. The first five bits have been factory pro-
grammed to 01011. The two address bits, AD1 and AD0,
are programmed by the user (see Function Table).
10-Bit Current Output DAC
The 10-Bit current output DAC is guaranteed monotonic
and is digitally adjustable in 1023 equal steps. On power-
up, if AD1 and AD0 are both connected to VCC, the 10-bit
internal register C (see Block Diagram) resets to
1000000000B and the DAC output is set to midrange. If
either AD1 or AD0 is connected to ground, register C
resets to 0000000000B on power-up and the DAC output
is set to zero. For the LTC1427-50, the source current
output (IOUT) can be biased from – 15V to (VCC – 1.3V).
Full-scale current is trimmed to
±1.5% at room tempera-
ture and
±2.5% over the commercial temperature range.
Shutdown
There are two ways to shut down the LTC1427-50 (see
Block Diagram). The LTC1427-50 will enter shutdown
mode whenever it sees a logic low at the SHDN pin or
whenever it receives a logic high at bit 7 of the command
byte through the SMBus interface. In shutdown mode, the
digital data is retained internally and the supply current
drops to only 10
A typically.
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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