参数资料
型号: LTC1503IS8-1.8#TR
厂商: Linear Technology
文件页数: 8/12页
文件大小: 0K
描述: IC REG BUCK SWITCHED CAP 8SOIC
标准包装: 2,500
类型: 降压(降压),切换电容(充电泵)
输出类型: 固定
输出数: 1
输出电压: 1.8V
输入电压: 2.4 V ~ 6 V
频率 - 开关: 600kHz
电流 - 输出: 100mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
供应商设备封装: 8-SOIC
LTC1503-1.8/LTC1503-2
APPLICATIO S I FOR ATIO
approximately 1.9V. Since the ramp rate on the SHDN/SS
pin controls the ramp rate on V OUT , the average inrush
current can be controlled through selection of C SS and
C OUT . For example, a 4.7nF capacitor on SHDN/SS results
in a 4ms ramp time from 0.35V to 1.9V on the pin. If C OUT
is 10 μ F, the 4ms V REF ramp time results in an average
C OUT charge current of only 5mA (see Figure 2c).
Capacitor Selection
For best performance, it is recommended that low ESR
capacitors be used for C IN and C OUT to reduce noise and
ripple. If the ESR of the output capacitor is too high
(> 0.5 ? ), both efficiency and output load regulation may
be degraded. The C IN and C OUT capacitors should be either
ceramic or tantalum and should be 10 μ F or greater. If the
input source impedance is very low (< 0.5 ? ), C IN may not
5
V OUT
LTC1503-X
SHDN/SS
1
R LOAD
be needed. Ceramic capacitors are recommended for the
flying caps C1 and C2 with values of 0.47 μ F to 2.2 μ F.
Smaller values may be used in low output current applica-
tions (e.g., I OUT < 10mA). For best performance choose
ON OFF V CTRL
C SS
1503-1.8/2 F02a
the same capacitance value for both C1 and C2.
Output Ripple
V CTRL
2V/DIV
V OUT
1V/DIV
(a)
Normal LTC1503-X operation produces voltage ripple on
the V OUT pin. Output voltage ripple is required for the parts
to regulate. Low frequency ripple exists due to the hyster-
esis in the sense comparator and propagation delays in the
charge pump enable/disable circuits. High frequency ripple
is also present mainly from the ESR (equivalent series
resistance) in the output capacitor. Typical output ripple
(V IN = 3.6V) under maximum load is 25mV peak-to-peak
with a low ESR 10 μ F output capacitor.
The magnitude of ripple voltage depends on several fac-
LTC1503-2
C SS = 0nF
C OUT = 10 μ F
R LOAD = 50 ?
2ms/DIV
(b)
1503-1.8/2 F02b
tors. High input voltages increase the output ripple since
more charge is delivered to C OUT per charging cycle. Large
output current load and/or a small output capacitor (< 10 μ F)
results in higher ripple due to higher output voltage dV/dt.
High ESR capacitors (ESR > 0.5 ? ) on the output pin cause
V CTRL
2V/DIV
V OUT
1V/DIV
high frequency voltage spikes on V OUT with every clock
cycle.
There are several ways to reduce the output voltage ripple
(see Figure 3). A larger C OUT capacitor (22 μ F or greater)
will reduce both the low and high frequency ripple due to
the lower C OUT charging and discharging dV/dt and the
lower ESR typically found with higher value (larger case
LTC1503-2
2ms/DIV
1503-1.8/2 F02b
size) capacitors. A low ESR ceramic output capacitor will
8
C SS = 4.7nF
C OUT = 10 μ F
R LOAD = 50 ?
(c)
Figure 2. Shutdown/Soft-Start Operation
minimize the high frequency ripple, but will not reduce the
low frequency ripple unless a high capacitance value is
chosen. A reasonable compromise is to use a 10 μ F to 22 μ F
tantalum capacitor in parallel with a 1 μ F to 3.3 μ F ceramic
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