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参数资料
| 型号： | LTC1536CS8#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 6/12页 |
| 文件大小： | 0K |
| 描述： | IC PREC TRPL SPPLY MONITOR 8SOIC |
| 标准包装： | 100 |
| 类型： | 多压监控器 |
| 监视电压数目： | 3 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 2.985V，4.725V，可调 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
| 产品目录页面： | 1337 (CN2011-ZH PDF) |
LTC1536
PI N FU N CTIO N S
V CC3 (Pin 1): 3.3V Sense Input and Power Supply Pin for
the IC. Bypass to ground with ≥ 0.1 μ F ceramic capacitor.
V CC5 (Pin 2): 5V Sense Input. Used as gate drive for RST
output FET when the voltage on V CC5 is greater than the
voltage on V CC3 .
V CCA (Pin 3): 1V Sense, High Impedance Input. Can be
used as a logic input with a 1V threshold. If unused it can
be tied to either V CC3 or V CC5 .
GND (Pin 4): Ground.
RST (Pin 5): Reset Logic Output. Active high CMOS logic
output, drives high to V CC3 , buffered compliment of RST.
An external pull-down on the RST pin will drive this pin high.
RST (Pin 6): Reset Logic Output. Active low, open-drain
logic output with weak pull-up to V CC3 . Can be pulled up
greater than V CC3 when interfacing to 5V logic.
BLOCK DIAGRA M
V CC3
Asserted when one or more of the supplies are below trip
thresholds and held for 200ms after all supplies become
valid. Also asserted after PBR is held low for more than two
seconds and for an additional 200ms after PBR is released.
SRST (Pin 7): “Soft” Reset. Active low, open-drain logic
output with weak pull-up to V CC3 . Can be pulled up greater
than V CC3 when interfacing to 5V logic. Asserted for 100 μ s
after PBR is held low for less than two seconds and released.
PBR (Pin 8): Pushbutton Reset. Active low logic input with
weak pull-up to V CC3 . Can be pulled up greater than V CC3
when interfacing to 5V logic. When asserted for less than
two seconds, outputs a soft reset 100 μ s pulse on the SRST
pin. When PBR is asserted for greater than two seconds,
the RST output is forced low and remains low until 200ms
after PBR is released.
V CC3
7 μ A
SOFT RESET
6 μ A
PBR 8
PBR
TIMER
RESET
7
SRST
TO POWER DETECT
AND V CC INTERNAL
V CC3 1
FAST
SLOW
V CC3
6 μ A
V CC3
FAST
200ms
RESET
GENERATOR
POWER
DETECT/
GATE DRIVE
6
RST
V CC3
V CC5 2
V CC5
5
RST
FAST
TO
POWER
DETECT
SLOW
V CCA 3
SLOW
GND 4
REF
1326 BD
1536fa
6
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