参数资料
型号: LTC1539IGW
厂商: Linear Technology
文件页数: 8/32页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 36-SSOP
标准包装: 32
PWM 型: 电流模式
输出数: 2
频率 - 最大: 138kHz
占空比: 99%
电源电压: 3.5 V ~ 30 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 36-BSOP(0.295",7.50mm 宽)
包装: 管件
LTC1538-AUX/LTC1539
PI N FU N CTIO N S
SENSE + 1, SENSE + 2: The (+) Input to Each Current
Comparator. Built-in offsets between SENSE – 1 and
SENSE + 1 pins in conjunction with R SENSE1 set the current
trip threshold (same for second controller).
V OSENSE2 : Receives the remotely sensed feedback voltage for
the second controller either from the output directly or from
an external resistive divider across the output . The V PROG2
pin determines which point. V OSENSE2 must connect to.
V PROG1 , V PROG2 : Programs Internal Voltage Attenuators
for Output Voltage Sensing. The voltage sensing for the
first controller is internally connected to SENSE – 1 while
the V OSENSE2 pin allows for remote sensing for the second
controller. For V PROG1 , V PROG2 < V INTVCC /3, the divider is
set for an output voltage of 3.3V. With V PROG1 ,
V PROG2 > V INTVCC /1.5 the divider is set for an output
voltage of 5V. Leaving V PROG2 open (DC) allows the output
voltage of the second controller to be set by an external
resistive divider connected to V OSENSE2 .
C OSC : External capacitor C OSC from this pin to ground sets
the operating frequency.
I TH1 , I TH2 : Error Amplifier Compensation Point. Each as-
sociated current comparator threshold increases with this
control voltage.
RUN/SS1, RUN/SS2: Combination of Soft Start and RUN
Control Inputs. A capacitor to ground at each of these pins
sets the ramp time to full current output. The time is
approximately 0.5s/ μ F. Forcing either of these pins below
1.3V causes the IC to shut down the circuitry required for
that particular controller. Forcing both of these pins below
1.3V causes the device to shut down both controllers,
leaving the 5V standby regulator, internal reference and a
comparator active. Refer to the LTC1438/LTC1439 for appli-
cations which do not require a 5V standby regulator.
TGL1, TGL2: High Current Gate Drives for Main Top
N-Channel MOSFET. These are the outputs of floating
drivers with a voltage swing equal to INTV CC superim-
posed on the switch node voltage SW1 and SW2.
TGS1, TGS2: Gate Drives for Small Top N-Channel
MOSFET. These are the outputs of floating drivers with a
voltage swing equal to INTV CC superimposed on the
switch node voltage SW. Leaving TGS1 or TGS2 open
invokes Burst Mode operation for that controller.
8
BG1, BG2: High Current Gate Drive Outputs for Bottom N-
Channel MOSFETs. Voltage swing at these pins is from
ground to INTV CC .
SFB1: Secondary Winding Feedback Input. This input acts
only on the first controller and is normally connected to a
feedback resistive divider from the secondary winding.
Pulling this pin below 1.19V will force continuous syn-
chronous operation for the first controller. This pin should
be tied to: ground to force continuous operation; INTV CC
in applications that don’t use a secondary winding; and a
resistive divider from the output in applications using a
secondary winding.
POR1: This output is a drain of an N-channel pull-down.
This pin sinks current when the output voltage of the first
controller drops 7.5% below its regulated voltage and re-
leases 65536 oscillator cycles after the output voltage of the
first controller rises to within –5% value of its regulated value.
The POR1 output is asserted when RUN/SS1 and RUN/SS2
are both low, independent of the V OUT1 .
LBO: This output is a drain of an N-channel pull-down. This
pin will sink current when the LBI pin goes below 1.19V
irrespective of the RUN/SS pin voltage.
LBI: The (+) input of a comparator which can be used as
a low-battery voltage detector irrespective of the RUN/SS
pin voltage. The (–) input is connected to the 1.19V
internal reference.
PLLIN: External Synchronizing Input to Phase Detector.
This pin is internally terminated to SGND with 50k ? . Tie
this pin to SGND in applications which do not use the
phase-locked loop.
PLL LPF: Output of Phase Detector and Control Input of
Oscillator. Normally a series RC lowpass filter network is
connected from this pin to ground. Tie this pin to SGND in
applications which do not use the phase-locked loop. Can
be driven by a 0V to 2.4V logic signal for a frequency
shifting option.
AUXFB: Feedback Input to the Auxiliary Regulator/Com-
parator. When used as a linear regulator, this input can
either be connected to an external resistive divider or
directly to the collector of the external PNP pass device for
12V operation. When used as a comparator, this is the
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