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| 型号： | LTC1553CSW#TR |
| 厂商： | Linear Technology |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC REG SW CTRLR 5BIT PROG 20SOIC |
| 标准包装： | 1,000 |
| 应用： | 控制器，Intel Pentium? II |
| 输入电压： | 5V，12V |
| 输出数： | 1 |
| 输出电压： | 1.8 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC |
| 包装： | 带卷 (TR) |
LTC1553
APPLICATIO N S I N FOR M ATIO N
complication of input and/or output filters, unknown
capacitor ESR, and gross operating point changes with
input voltage, load current variations, all suggest a more
practical empirical method. This can be done by injecting
a transient current at the load and using an RC network box
to iterate toward the final compensation values, or by
obtaining the optimum loop response using a network
analyzer to find the actual loop poles and zeros.
Table 6. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 330 μ F AVX TPS Output
Capacitors
L O ( μ H) C O ( μ F) R C (k ? ) C C ( μ F) C1 (pF)
1 990 1.8 0.022 680
1 1980 3.6 0.01 330
1 4950 9.1 0.01 120
2.7 990 5.1 0.01 220
2.7 1980 10 0.01 120
2.7 4950 24 0.0047 47
5.6 990 10 0.01 120
5.6 1980 20 0.0047 56
5.6 4950 51 0.0036 22
Table 7. Suggested Compensation Network for 12V Input
Application Using Multiple Paralleled 330 μ F AVX TPS Output
Capacitors
L O ( μ H) C O ( μ F) R C (k ? ) C C ( μ F) C1 (pF)
the suggested values slightly because of board layout and
operating condition differences.
An alternate output capacitor is the Sanyo MV-GX series.
Using multiple parallel 1500 μ F Sanyo MV-GX capacitors
for the output capacitor, Table 8 shows the suggested
compensation component value for a 5V input application
based on the inductor and output capacitor values.
Table 8. Suggested Compensation Network for 5V Input
Application Using Multiple Paralleled 1500 μ F SANYO MV-GX
Output Capacitors
L O ( μ H) C O ( μ F) R C (k ? ) C C ( μ F) C1 (pF)
1 4500 4.3 0.022 270
1 6000 5.6 0.0047 220
1 9000 8.2 0.01 150
2.7 4500 11 0.01 100
2.7 6000 15 0.01 82
2.7 9000 22 0.01 56
5.6 4500 24 0.01 56
5.6 6000 30 0.0047 39
5.6 9000 47 0.0047 27
VID0 to VID4, PWRGD and FAULT
The digital inputs (VID0 to VID4) program the internal DAC
which in turn controls the output voltage. These digital
1
1
1
2.7
2.7
2.7
5.6
5.6
5.6
990
1980
4950
990
1980
4950
990
1980
4950
0.82
1.5
3.9
2.2
4.3
10
4.3
8.2
22
0.047
0.033
0.022
0.033
0.022
0.01
0.022
0.010
0.010
1500
820
330
560
270
120
270
150
56
input controls are intended to be static and are not
designed for high speed switching. Forcing V OUT to step
from a high to a low voltage by changing the VID n pins
quickly can cause FAULT to trip.
Figure 11 shows the relationship between the V OUT volt-
age, PWRGD and FAULT. To prevent PWRGD from inter-
rupting the CPU unnecessarily, the LTC1553 has a built-in
t PWRBAD delay to prevent noise at the SENSE pin from
toggling PWRGD. The internal time delay is designed to
take about 500 μ s for PWRGD to go low and 1ms for it to
Tables 6 and 7 show the suggested compensation com-
ponents for 5V and 12V input applications based on the
inductor and output capacitor values. The values were
calculated using multiple paralleled 330 μ F AVX TPS series
surface mount tantalum capacitors as the output capaci-
tor. The optimum component values might deviate from
18
recover. Once PWRGD goes low, the internal circuitry
watches for the output voltage to exceed 115% of the rated
voltage. If this happens, FAULT will be triggered. Once
FAULT is triggered, G1 and G2 will be forced low immedi-
ately and the LTC1553 will remain in this state until V CC
power supply is recycled or OUTEN is toggled.
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