参数资料
型号: LTC1605-1IG#PBF
厂商: Linear Technology
文件页数: 18/20页
文件大小: 0K
描述: IC A/D CONV 16BIT SAMPLNG 28SSOP
标准包装: 47
位数: 16
采样率(每秒): 100k
数据接口: 并联
转换器数目: 1
功率耗散(最大): 80mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 管件
输入数目和类型: 1 个单端,双极
配用: DC1255A-A-ND - BOARD SAR ADC LTC1605
7
LTC1605-1/LTC1605-2
APPLICATIONS INFORMATION
WU
U
autozero switch, S3. In this acquire phase, a minimum
delay of 2
swillprovideenoughtimeforthesample-and-
hold capacitor to acquire the analog signal. During the
convert phase, S3 opens, putting the comparator into the
compare mode. The input switch S2 switches CSAMPLE to
ground, injecting the analog input charge onto the sum-
ming junction. This input charge is successively com-
pared with the binary-weighted charges supplied by the
capacitive DAC. Bit decisions are made by the high speed
comparator. At the end of a conversion, the DAC output
balances the VIN input charge. The SAR contents (a 16-
bit data word) that represents the VIN are loaded into the
16-bit output latches.
Driving the Analog Inputs
The nominal input range for the LTC1605-1 is 0V to 4V or
(1.6VREF) and for the LTC1605-2 the input range is ±4V
or (
±1.6VREF). The inputs are overvoltage protected to
±25V. The input impedance is typically 10k; therefore,
it should be driven by a low impedance source. Wideband
noise coupling into the input can be minimized by placing
a 1000pF capacitor at the input as shown in Figure 2. An
NPO-type capacitor gives the lowest distortion. Place the
capacitor as close to the device input pin as possible. If
an amplifier is to be used to drive the input, care should
be taken to select an amplifier with adequate accuracy,
linearity and noise for the application. The following list
is a summary of the op amps that are suitable for driving
the LTC1605-1/LTC1605-2. More detailed information is
available in the Linear Technology data books and
LinearView
TM CD-ROM.
Conversion Details
The LTC1605-1/LTC1605-2 use a successive approxi-
mation algorithm and an internal sample-and-hold cir-
cuit to convert an analog signal to a 16-bit or two byte
parallel output. The ADC is complete with a precision
reference and an internal clock. The control logic pro-
vides easy interface to microprocessors and DSPs. (Please
refer to the Digital Interface section for the data format.)
Conversion start is controlled by the CS and R/C inputs.
At the start of conversion, the successive approximation
register (SAR) is reset. Once a conversion cycle has
begun, it cannot be restarted.
During the conversion, the internal 16-bit capacitive DAC
output is sequenced by the SAR from the most significant
bit (MSB) to the least significant bit (LSB). Referring to
Figure 1, VIN is connected through the resistor divider
and S1 to the sample-and-hold capacitor during the
acquire phase and the comparator offset is nulled by the
Figure 1. LTC1605-1/LTC1605-2 Simplified Equivalent Circuit
VDAC
1605-1/2 F01
+
CDAC
DAC
S1
SAMPLE
S2
HOLD
CSAMPLE
S
A
R
16-BIT
LATCH
COMPARATOR
SAMPLE
S3
RIN2
RIN1
VIN
LinearView is a trademark of Linear Technology Corporation
1k
50pF
DBN
1k
5V
1605-1/2 TC02
A. VOH TO HI-Z
B. VOL TO HI-Z
Load Circuit for Access Timing
Load Circuit for Output Float Delay
1k
CL
DBN
1k
5V
1605-1/2 TC01
A. HI-Z TO VOH AND VOL TO VOH
B. HI-Z TO VOL AND VOH TO VOL
TEST CIRCUITS
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